From b7a7e2bfc9759301e1229c773416b1745e5e845c Mon Sep 17 00:00:00 2001 From: xubilv Date: Mon, 28 Mar 2016 14:53:30 +0800 Subject: [PATCH] video: rockchip: mipi: enable clk before write register Change-Id: I717ed1143c53e7c2cd04697e8cc3984f89e29504 Signed-off-by: xubilv --- drivers/video/rockchip/transmitter/rk32_mipi_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c index 4dd8f187b5f7..018cb0810a3d 100755 --- a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c +++ b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c @@ -457,7 +457,6 @@ static void rk312x_mipi_dsi_set_hs_clk(struct dsi *dsi) static int rk312x_phy_power_up(struct dsi *dsi) { /* enable ref clock */ - rk312x_mipi_dsi_set_hs_clk(dsi); clk_prepare_enable(dsi->phy.refclk); clk_prepare_enable(dsi->dsi_pclk); clk_prepare_enable(dsi->dsi_host_pclk); @@ -466,6 +465,7 @@ static int rk312x_phy_power_up(struct dsi *dsi) udelay(10); + rk312x_mipi_dsi_set_hs_clk(dsi); rk32_dsi_set_bits(dsi, 0xe4, DPHY_REGISTER1); switch (dsi->host.lane) { case 4: -- 2.34.1