From b7c19b3cc9f1754461dc756f907b9b438b830546 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 31 Mar 2015 13:32:32 +0000 Subject: [PATCH] Revert 233694. Weak SVN-fu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233695 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/CMakeLists.txt | 1 - lib/Target/Hexagon/HexagonInstrInfo.cpp | 5 +++-- lib/Target/Hexagon/HexagonInstrInfo.h | 4 +++- lib/Target/Hexagon/HexagonTargetMachine.cpp | 24 ++++----------------- test/CodeGen/Hexagon/adde.ll | 2 +- test/CodeGen/Hexagon/sube.ll | 2 +- test/MC/Hexagon/inst_select.ll | 2 +- 7 files changed, 13 insertions(+), 27 deletions(-) diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index 758ccc74100..c6ffb96609e 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -15,7 +15,6 @@ add_llvm_target(HexagonCodeGen HexagonAsmPrinter.cpp HexagonCFGOptimizer.cpp HexagonCopyToCombine.cpp - HexagonExpandCondsets.cpp HexagonExpandPredSpillCode.cpp HexagonFixupHwLoops.cpp HexagonFrameLowering.cpp diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index ff4bcadaabb..fbf1ca90055 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -845,7 +845,8 @@ bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const { return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask); } -int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const { +int HexagonInstrInfo:: +getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { enum Hexagon::PredSense inPredSense; inPredSense = invertPredicate ? Hexagon::PredSense_false : Hexagon::PredSense_true; @@ -883,7 +884,7 @@ PredicateInstruction(MachineInstr *MI, // This will change MI's opcode to its predicate version. // However, its operand list is still the old one, i.e. the // non-predicate one. - MI->setDesc(get(getCondOpcode(Opc, invertJump))); + MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump))); int oper = -1; unsigned int GAIdx = 0; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 284dde1f91e..264424867dc 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -216,7 +216,9 @@ public: short getNonExtOpcode(const MachineInstr *MI) const; bool PredOpcodeHasJMP_c(Opcode_t Opcode) const; bool PredOpcodeHasNot(Opcode_t Opcode) const; - int getCondOpcode(int Opc, bool sense) const; + +private: + int getMatchingCondBranchOpcode(int Opc, bool sense) const; }; diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 06798665cb0..48b0bc8baf3 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -27,15 +27,11 @@ using namespace llvm; static cl:: opt DisableHardwareLoops("disable-hexagon-hwloops", - cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); + cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); static cl::opt DisableHexagonCFGOpt("disable-hexagon-cfgopt", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Disable Hexagon CFG Optimization")); - -static cl::opt EnableExpandCondsets("hexagon-expand-condsets", - cl::init(true), cl::Hidden, cl::ZeroOrMore, - cl::desc("Early expansion of MUX")); + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Disable Hexagon CFG Optimization")); /// HexagonTargetMachineModule - Note that this is used on hosts that @@ -59,10 +55,6 @@ static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched); -namespace llvm { - FunctionPass *createHexagonExpandCondsets(); -} - /// HexagonTargetMachine ctor - Create an ILP32 architecture model. /// @@ -87,15 +79,7 @@ namespace { class HexagonPassConfig : public TargetPassConfig { public: HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) { - bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None); - if (!NoOpt) { - if (EnableExpandCondsets) { - Pass *Exp = createHexagonExpandCondsets(); - insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp)); - } - } - } + : TargetPassConfig(TM, PM) {} HexagonTargetMachine &getHexagonTargetMachine() const { return getTM(); diff --git a/test/CodeGen/Hexagon/adde.ll b/test/CodeGen/Hexagon/adde.ll index 5a8345c477c..6d060c1b9e2 100644 --- a/test/CodeGen/Hexagon/adde.ll +++ b/test/CodeGen/Hexagon/adde.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s +; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+:[0-9]+}} = #0 ; CHECK: r{{[0-9]+:[0-9]+}} = #1 diff --git a/test/CodeGen/Hexagon/sube.ll b/test/CodeGen/Hexagon/sube.ll index 1a7882276c8..735ac9eb82e 100644 --- a/test/CodeGen/Hexagon/sube.ll +++ b/test/CodeGen/Hexagon/sube.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s +; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+:[0-9]+}} = #0 ; CHECK: r{{[0-9]+:[0-9]+}} = #1 diff --git a/test/MC/Hexagon/inst_select.ll b/test/MC/Hexagon/inst_select.ll index 29a2db0723b..7e88c65a818 100644 --- a/test/MC/Hexagon/inst_select.ll +++ b/test/MC/Hexagon/inst_select.ll @@ -7,4 +7,4 @@ define i32 @foo (i1 %a, i32 %b, i32 %c) ret i32 %1 } -; CHECK: 0000 00400085 00600174 00608274 00c09f52 +; CHECK: 0000 00400085 004201f4 00c09f52 -- 2.34.1