From b8a0c8e3f22e06bef5b3091dea10c45289af09d0 Mon Sep 17 00:00:00 2001 From: chenxing Date: Sun, 6 Jan 2013 14:24:35 +0800 Subject: [PATCH] rk2928: fix too many usb hub irqs when changing frequency --- arch/arm/mach-rk2928/clock_data.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rk2928/clock_data.c b/arch/arm/mach-rk2928/clock_data.c index 084776e2ae77..346ad8f2e09e 100644 --- a/arch/arm/mach-rk2928/clock_data.c +++ b/arch/arm/mach-rk2928/clock_data.c @@ -123,6 +123,7 @@ struct pll_clk_set { .pllcon2 = PLL_SET_FRAC(_frac), \ .clksel1 = ACLK_CORE_DIV(RATIO_##_aclk_core_div) | CLK_CORE_PERI_DIV(RATIO_##_periph_div), \ .lpj = (CLK_LOOPS_JIFFY_REF * _mhz) / CLK_LOOPS_RATE_REF, \ + .rst_dly = 0,\ } static const struct apll_clk_set apll_clks[] = { @@ -751,7 +752,7 @@ static int pll_set_con(u8 id, u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2, temp_clk_set.pllcon1 |= PLL_SET_DSMPD(1); } temp_clk_set.pllcon2 = PLL_SET_FRAC(frac); - temp_clk_set.rst_dly = 1500; + temp_clk_set.rst_dly = 0; CLKDATA_DBG("setting....\n"); return pll_clk_set_rate(&temp_clk_set, id); } @@ -795,7 +796,7 @@ static int apll_clk_set_rate(struct clk *clk, unsigned long rate) cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2)); cru_writel(clk_set->clksel0, CRU_CLKSELS_CON(0)); cru_writel(clk_set->clksel1, CRU_CLKSELS_CON(1)); - local_irq_restore(flags); + //local_irq_restore(flags); CLKDATA_DBG("pllcon0 %08x\n", cru_readl(PLL_CONS(0,0))); CLKDATA_DBG("pllcon1 %08x\n", cru_readl(PLL_CONS(0,1))); @@ -810,7 +811,7 @@ static int apll_clk_set_rate(struct clk *clk, unsigned long rate) pll_wait_lock(pll_id); //return form slow - local_irq_save(flags); + //local_irq_save(flags); cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON); loops_per_jiffy = clk_set->lpj; local_irq_restore(flags); -- 2.34.1