From bb0572a5d118ba2ca82738c00ea9913033258234 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Mon, 7 Apr 2014 22:11:40 +0000 Subject: [PATCH] Reverting commit r205628 due to mips64 issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205741 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.cpp | 70 ++++++++++++++++++++++++++++ lib/Target/Mips/MipsInstrFPU.td | 2 +- lib/Target/Mips/MipsInstrInfo.td | 3 +- test/CodeGen/Mips/fabs.ll | 47 +++++++++++++------ test/CodeGen/Mips/fmadd1.ll | 15 ------ test/CodeGen/Mips/fneg.ll | 24 +++------- 6 files changed, 112 insertions(+), 49 deletions(-) diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index c6533e8c47d..1f45d1d0559 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -245,6 +245,11 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + if (!TM.Options.NoNaNsFPMath) { + setOperationAction(ISD::FABS, MVT::f32, Custom); + setOperationAction(ISD::FABS, MVT::f64, Custom); + } + if (hasMips64()) { setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::BlockAddress, MVT::i64, Custom); @@ -329,6 +334,11 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::FREM, MVT::f32, Expand); setOperationAction(ISD::FREM, MVT::f64, Expand); + if (!TM.Options.NoNaNsFPMath) { + setOperationAction(ISD::FNEG, MVT::f32, Expand); + setOperationAction(ISD::FNEG, MVT::f64, Expand); + } + setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); setOperationAction(ISD::VAARG, MVT::Other, Expand); @@ -769,6 +779,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const case ISD::SETCC: return lowerSETCC(Op, DAG); case ISD::VASTART: return lowerVASTART(Op, DAG); case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); + case ISD::FABS: return lowerFABS(Op, DAG); case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); @@ -1760,6 +1771,65 @@ MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert()); } +static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, + bool HasExtractInsert) { + SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); + SDLoc DL(Op); + + // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it + // to i32. + SDValue X = (Op.getValueType() == MVT::f32) ? + DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : + DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), + Const1); + + // Clear MSB. + if (HasExtractInsert) + Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, + DAG.getRegister(Mips::ZERO, MVT::i32), + DAG.getConstant(31, MVT::i32), Const1, X); + else { + SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); + Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); + } + + if (Op.getValueType() == MVT::f32) + return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); + + SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, + Op.getOperand(0), DAG.getConstant(0, MVT::i32)); + return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); +} + +static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, + bool HasExtractInsert) { + SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); + SDLoc DL(Op); + + // Bitcast to integer node. + SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); + + // Clear MSB. + if (HasExtractInsert) + Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, + DAG.getRegister(Mips::ZERO_64, MVT::i64), + DAG.getConstant(63, MVT::i32), Const1, X); + else { + SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); + Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); + } + + return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); +} + +SDValue +MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { + if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) + return lowerFABS64(Op, DAG, Subtarget->hasExtractInsert()); + + return lowerFABS32(Op, DAG, Subtarget->hasExtractInsert()); +} + SDValue MipsTargetLowering:: lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { // check the depth diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 71c27572ef0..4b5a73ef77a 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -322,7 +322,7 @@ let isPseudo = 1, isCodeGenOnly = 1 in { def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; } -let Predicates = [HasStdEnc] in { +let Predicates = [NoNaNsFPMath, HasStdEnc] in { def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, ABSS_FM<0x5, 16>; def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 9a37194c787..07c37d87a26 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -176,7 +176,8 @@ def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, AssemblerPredicate<"FeatureMips32">; def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, AssemblerPredicate<"FeatureMips32">; -def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; +def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, + AssemblerPredicate<"FeatureMips32">; def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, AssemblerPredicate<"!FeatureMips16">; def NotDSP : Predicate<"!Subtarget.hasDSP()">; diff --git a/test/CodeGen/Mips/fabs.ll b/test/CodeGen/Mips/fabs.ll index 7516ec90cc3..49d8a7201e8 100644 --- a/test/CodeGen/Mips/fabs.ll +++ b/test/CodeGen/Mips/fabs.ll @@ -1,20 +1,21 @@ -; Check that abs.[ds] is selected and does not depend on -enable-no-nans-fp-math -; They obey the Has2008 and ABS2008 configuration bits which govern the -; conformance to IEEE 754 (1985) and IEEE 754 (2008). When these bits are not -; present, they confirm to 1985. -; In 1985 mode, abs.[ds] are arithmetic (i.e. they raise invalid operation -; exceptions when given NaN's). In 2008 mode, they are non-arithmetic (i.e. -; they are copies and don't raise any exceptions). - -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s -check-prefix=32 +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN define float @foo0(float %a) nounwind readnone { entry: -; CHECK-LABEL: foo0 -; CHECK: abs.s +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: mtc1 $[[AND]], $f0 + +; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1 +; 32R2: mtc1 $[[INS]], $f0 + +; NO-NAN: abs.s %call = tail call float @fabsf(float %a) nounwind readnone ret float %call @@ -25,8 +26,24 @@ declare float @fabsf(float) nounwind readnone define double @foo1(double %a) nounwind readnone { entry: -; CHECK-LABEL: foo1: -; CHECK: abs.d +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: mtc1 $[[AND]], $f1 + +; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1 +; 32R2: mtc1 $[[INS]], $f1 + +; 64: daddiu $[[T0:[0-9]+]], $zero, 1 +; 64: dsll $[[T1:[0-9]+]], ${{[0-9]+}}, 63 +; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 +; 64: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: dmtc1 $[[AND]], $f0 + +; 64R2: dins $[[INS:[0-9]+]], $zero, 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 + +; NO-NAN: abs.d %call = tail call double @fabs(double %a) nounwind readnone ret double %call diff --git a/test/CodeGen/Mips/fmadd1.ll b/test/CodeGen/Mips/fmadd1.ll index a9a8e212e49..6768ed66902 100644 --- a/test/CodeGen/Mips/fmadd1.ll +++ b/test/CodeGen/Mips/fmadd1.ll @@ -1,10 +1,3 @@ -; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported -; correctly. -; The spec for nmadd.[ds], and nmsub.[ds] does not state that they obey the -; the Has2008 and ABS2008 configuration bits which govern the conformance to -; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only -; available when -enable-no-nans-fp-math is given. - ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=32R2 -check-prefix=CHECK ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=64R2 -check-prefix=CHECK ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2NAN -check-prefix=CHECK @@ -12,7 +5,6 @@ define float @FOO0float(float %a, float %b, float %c) nounwind readnone { entry: -; CHECK-LABEL: FOO0float: ; CHECK: madd.s %mul = fmul float %a, %b %add = fadd float %mul, %c @@ -22,7 +14,6 @@ entry: define float @FOO1float(float %a, float %b, float %c) nounwind readnone { entry: -; CHECK-LABEL: FOO1float: ; CHECK: msub.s %mul = fmul float %a, %b %sub = fsub float %mul, %c @@ -32,7 +23,6 @@ entry: define float @FOO2float(float %a, float %b, float %c) nounwind readnone { entry: -; CHECK-LABEL: FOO2float: ; 32R2: nmadd.s ; 64R2: nmadd.s ; 32R2NAN: madd.s @@ -45,7 +35,6 @@ entry: define float @FOO3float(float %a, float %b, float %c) nounwind readnone { entry: -; CHECK-LABEL: FOO3float: ; 32R2: nmsub.s ; 64R2: nmsub.s ; 32R2NAN: msub.s @@ -58,7 +47,6 @@ entry: define double @FOO10double(double %a, double %b, double %c) nounwind readnone { entry: -; CHECK-LABEL: FOO10double: ; CHECK: madd.d %mul = fmul double %a, %b %add = fadd double %mul, %c @@ -68,7 +56,6 @@ entry: define double @FOO11double(double %a, double %b, double %c) nounwind readnone { entry: -; CHECK-LABEL: FOO11double: ; CHECK: msub.d %mul = fmul double %a, %b %sub = fsub double %mul, %c @@ -78,7 +65,6 @@ entry: define double @FOO12double(double %a, double %b, double %c) nounwind readnone { entry: -; CHECK-LABEL: FOO12double: ; 32R2: nmadd.d ; 64R2: nmadd.d ; 32R2NAN: madd.d @@ -91,7 +77,6 @@ entry: define double @FOO13double(double %a, double %b, double %c) nounwind readnone { entry: -; CHECK-LABEL: FOO13double: ; 32R2: nmsub.d ; 64R2: nmsub.d ; 32R2NAN: msub.d diff --git a/test/CodeGen/Mips/fneg.ll b/test/CodeGen/Mips/fneg.ll index d8fd35c6b6f..b322abdaa23 100644 --- a/test/CodeGen/Mips/fneg.ll +++ b/test/CodeGen/Mips/fneg.ll @@ -1,27 +1,17 @@ -; Check that abs.[ds] is selected and does not depend on -enable-no-nans-fp-math -; They obey the Has2008 and ABS2008 configuration bits which govern the -; conformance to IEEE 754 (1985) and IEEE 754 (2008). When these bits are not -; present, they confirm to 1985. -; In 1985 mode, abs.[ds] are arithmetic (i.e. they raise invalid operation -; exceptions when given NaN's). In 2008 mode, they are non-arithmetic (i.e. -; they are copies and don't raise any exceptions). +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s - -define float @foo0(float %d) nounwind readnone { +define float @foo0(i32 %a, float %d) nounwind readnone { entry: -; CHECK-LABEL: foo0: -; CHECK: neg.s +; CHECK-NOT: neg.s %sub = fsub float -0.000000e+00, %d ret float %sub } -define double @foo1(double %d) nounwind readnone { +define double @foo1(i32 %a, double %d) nounwind readnone { entry: -; CHECK-LABEL: foo1: -; CHECK: neg.d +; CHECK: foo1 +; CHECK-NOT: neg.d +; CHECK: jr %sub = fsub double -0.000000e+00, %d ret double %sub } -- 2.34.1