From bb5a039b76cc2cc6de6a5b6bdd4ebf6aefd9d564 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Thu, 2 Sep 2010 18:18:52 +0000
Subject: [PATCH] handle case where a register class is specified

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112842 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/TargetRegisterInfo.cpp | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp
index cdbe51fbdd9..6addbab851e 100644
--- a/lib/Target/TargetRegisterInfo.cpp
+++ b/lib/Target/TargetRegisterInfo.cpp
@@ -74,12 +74,11 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
   BitVector Allocatable(NumRegs);
   if (RC) {
     getAllocatableSetForRC(MF, RC, Allocatable);
-    return Allocatable;
-  }
-
-  for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
+  } else {
+    for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
          E = regclass_end(); I != E; ++I)
-    getAllocatableSetForRC(MF, *I, Allocatable);
+      getAllocatableSetForRC(MF, *I, Allocatable);
+  }
 
   // Mask out the reserved registers
   BitVector Reserved = getReservedRegs(MF);
-- 
2.34.1