From bc89e85f8744002ffde46233498afe13e42d7c93 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Tue, 12 Jul 2011 20:31:58 +0800 Subject: [PATCH] rk29: clock: increase aclk_cpu for 1G+ --- arch/arm/mach-rk29/clock.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c index cab1bb96f360..89a01e747d1d 100755 --- a/arch/arm/mach-rk29/clock.c +++ b/arch/arm/mach-rk29/clock.c @@ -411,9 +411,9 @@ struct arm_pll_set { static const struct arm_pll_set arm_pll[] = { // rate = 24 * NF / (NR * NO) // rate NR NF NO adiv hdiv pdiv - ARM_PLL(1200, 1, 50, 1, 41, 21, 81), - ARM_PLL(1104, 1, 46, 1, 41, 21, 81), - ARM_PLL(1008, 1, 42, 1, 41, 21, 81), + ARM_PLL(1200, 1, 50, 1, 31, 21, 81), + ARM_PLL(1104, 1, 46, 1, 31, 21, 81), + ARM_PLL(1008, 1, 42, 1, 31, 21, 81), ARM_PLL( 912, 1, 38, 1, 31, 21, 81), ARM_PLL( 888, 2, 74, 1, 31, 21, 81), ARM_PLL( 816, 1, 34, 1, 31, 21, 81), @@ -2635,7 +2635,7 @@ void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz", arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ, aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ); - printk(KERN_CONT " (20110711)\n"); + printk(KERN_CONT " (20110712)\n"); } void __init rk29_clock_init(enum periph_pll ppll_rate) -- 2.34.1