From bcea4d6f283a5ae6f93dc8e10898311fe53d23a3 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 2 Jan 2005 02:37:07 +0000 Subject: [PATCH] Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19247 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrInfo.cpp | 81 +++++++++++++++++++++++++++++++++ lib/Target/X86/X86InstrInfo.h | 12 +++++ 2 files changed, 93 insertions(+) diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 42b0ec95a87..d588afe28af 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -13,6 +13,7 @@ #include "X86InstrInfo.h" #include "X86.h" +#include "X86InstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "X86GenInstrInfo.inc" using namespace llvm; @@ -39,6 +40,83 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, return false; } +/// convertToThreeAddress - This method must be implemented by targets that +/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target +/// may be able to convert a two-address instruction into a true +/// three-address instruction on demand. This allows the X86 target (for +/// example) to convert ADD and SHL instructions into LEA instructions if they +/// would require register copies due to two-addressness. +/// +/// This method returns a null pointer if the transformation cannot be +/// performed, otherwise it returns the new instruction. +/// +MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const { + // All instructions input are two-addr instructions. Get the known operands. + unsigned Dest = MI->getOperand(0).getReg(); + unsigned Src = MI->getOperand(1).getReg(); + + // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When + // we have subtarget support, enable the 16-bit LEA generation here. + bool DisableLEA16 = true; + + switch (MI->getOpcode()) { + case X86::INC32r: + assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); + return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1); + case X86::INC16r: + if (DisableLEA16) return 0; + assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); + return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1); + case X86::DEC32r: + assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); + return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1); + case X86::DEC16r: + if (DisableLEA16) return 0; + assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); + return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1); + case X86::ADD32rr: + assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); + return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src, + MI->getOperand(2).getReg()); + case X86::ADD16rr: + if (DisableLEA16) return 0; + assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); + return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src, + MI->getOperand(2).getReg()); + case X86::ADD32ri: + assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); + if (MI->getOperand(2).isImmediate()) + return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, + MI->getOperand(2).getImmedValue()); + return 0; + case X86::ADD16ri: + if (DisableLEA16) return 0; + assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); + if (MI->getOperand(2).isImmediate()) + return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, + MI->getOperand(2).getImmedValue()); + break; + + case X86::SHL16ri: + if (DisableLEA16) return 0; + case X86::SHL32ri: + assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() && + "Unknown shl instruction!"); + unsigned ShAmt = MI->getOperand(2).getImmedValue(); + if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { + X86AddressMode AM; + AM.Scale = 1 << ShAmt; + AM.IndexReg = Src; + unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; + return addFullAddress(BuildMI(Opc, 5, Dest), AM); + } + break; + } + + return 0; +} + + void X86InstrInfo::insertGoto(MachineBasicBlock& MBB, MachineBasicBlock& TMBB) const { BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB); @@ -59,6 +137,8 @@ X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const { case X86::JA: ROpcode = X86::JBE; break; case X86::JS: ROpcode = X86::JNS; break; case X86::JNS: ROpcode = X86::JS; break; + case X86::JP: ROpcode = X86::JNP; break; + case X86::JNP: ROpcode = X86::JP; break; case X86::JL: ROpcode = X86::JGE; break; case X86::JGE: ROpcode = X86::JL; break; case X86::JLE: ROpcode = X86::JG; break; @@ -68,3 +148,4 @@ X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const { MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock(); return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB); } + diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 72eee6bc3ee..c8f8716fcda 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -179,6 +179,18 @@ public: unsigned& sourceReg, unsigned& destReg) const; + /// convertToThreeAddress - This method must be implemented by targets that + /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target + /// may be able to convert a two-address instruction into a true + /// three-address instruction on demand. This allows the X86 target (for + /// example) to convert ADD and SHL instructions into LEA instructions if they + /// would require register copies due to two-addressness. + /// + /// This method returns a null pointer if the transformation cannot be + /// performed, otherwise it returns the new instruction. + /// + virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; + /// Insert a goto (unconditional branch) sequence to TMBB, at the /// end of MBB virtual void insertGoto(MachineBasicBlock& MBB, -- 2.34.1