From bd0781ed12dd817f760065e3ac2dcff12fb29440 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 11 Apr 2005 20:29:59 +0000 Subject: [PATCH] Teach the dag mechanism that this: long long test2(unsigned A, unsigned B) { return ((unsigned long long)A << 32) + B; } is equivalent to this: long long test1(unsigned A, unsigned B) { return ((unsigned long long)A << 32) | B; } Now they are both codegen'd to this on ppc: _test2: blr or this on x86: test2: movl 4(%esp), %edx movl 8(%esp), %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21231 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index e4213171724..a9329cf8769 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1443,8 +1443,27 @@ ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, ExpandOp(LHS, LHSL, LHSH); ExpandOp(RHS, RHSL, RHSH); - // Convert this add to the appropriate ADDC pair. The low part has no carry - // in. + // FIXME: this should be moved to the dag combiner someday. + if (NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS) + if (LHSL.getValueType() == MVT::i32) { + SDOperand LowEl; + if (ConstantSDNode *C = dyn_cast(LHSL)) + if (C->getValue() == 0) + LowEl = RHSL; + if (ConstantSDNode *C = dyn_cast(RHSL)) + if (C->getValue() == 0) + LowEl = LHSL; + if (LowEl.Val) { + // Turn this into an add/sub of the high part only. + SDOperand HiEl = + DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB, + LowEl.getValueType(), LHSH, RHSH); + Lo = LowEl; + Hi = HiEl; + return; + } + } + std::vector Ops; Ops.push_back(LHSL); Ops.push_back(LHSH); -- 2.34.1