From bd9ac2a8d9000e2ab7c0caaf824beff46a54635a Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Thu, 29 Aug 2013 15:05:43 +0800 Subject: [PATCH] rk: support dcache disable --- arch/arm/include/asm/atomic.h | 2 +- arch/arm/include/asm/locks.h | 2 +- arch/arm/include/asm/system.h | 6 +++--- arch/arm/kernel/entry-armv.S | 2 +- arch/arm/lib/bitops.h | 2 +- arch/arm/mm/Kconfig | 2 ++ 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 7e79503ab89b..16d92e837c53 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -27,7 +27,7 @@ #define atomic_read(v) (*(volatile int *)&(v)->counter) #define atomic_set(v,i) (((v)->counter) = (i)) -#if __LINUX_ARM_ARCH__ >= 6 +#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE) /* * ARMv6 UP and SMP safe atomic ops. We use load exclusive and diff --git a/arch/arm/include/asm/locks.h b/arch/arm/include/asm/locks.h index ef4c897772d1..82df16603b8f 100644 --- a/arch/arm/include/asm/locks.h +++ b/arch/arm/include/asm/locks.h @@ -12,7 +12,7 @@ #ifndef __ASM_PROC_LOCKS_H #define __ASM_PROC_LOCKS_H -#if __LINUX_ARM_ARCH__ >= 6 +#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE) #define __down_op(ptr,fail) \ ({ \ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 832888d0c20c..bb3bc5beb66d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -269,14 +269,14 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size #ifdef swp_is_buggy unsigned long flags; #endif -#if __LINUX_ARM_ARCH__ >= 6 +#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE) unsigned int tmp; #endif smp_mb(); switch (size) { -#if __LINUX_ARM_ARCH__ >= 6 +#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE) case 1: asm volatile("@ __xchg1\n" "1: ldrexb %0, [%3]\n" @@ -346,7 +346,7 @@ void cpu_idle_wait(void); #include -#if __LINUX_ARM_ARCH__ < 6 +#if __LINUX_ARM_ARCH__ < 6 || defined(CONFIG_CPU_DCACHE_DISABLE) /* min ARCH < ARMv6 */ #ifdef CONFIG_SMP diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 2cd00764016d..53f63061825b 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -905,7 +905,7 @@ __kuser_cmpxchg: @ 0xffff0fc0 ldmfd sp!, {r7, pc} 1: .word __ARM_NR_cmpxchg -#elif __LINUX_ARM_ARCH__ < 6 +#elif __LINUX_ARM_ARCH__ < 6 || defined(CONFIG_CPU_DCACHE_DISABLE) #ifdef CONFIG_MMU diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h index 10d868a5a481..679c981ee5f0 100644 --- a/arch/arm/lib/bitops.h +++ b/arch/arm/lib/bitops.h @@ -1,4 +1,4 @@ -#if __LINUX_ARM_ARCH__ >= 6 +#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE) .macro bitop, instr ands ip, r1, #3 strneb r1, [ip] @ assert word-aligned diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index acb1c36adadd..a4818f129bd2 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -721,6 +721,8 @@ config CPU_ICACHE_DISABLE config CPU_DCACHE_DISABLE bool "Disable D-Cache (C-bit)" depends on CPU_CP15 + depends on !SMP && !SWP_EMULATE + select GENERIC_ATOMIC64 help Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N. -- 2.34.1