From bede187814039e6788179c883e753666420fac3b Mon Sep 17 00:00:00 2001 From: yxj Date: Wed, 26 Feb 2014 11:03:21 +0800 Subject: [PATCH] edp anx6345: add dpcd&edid read support --- drivers/video/rockchip/transmitter/anx6345.h | 932 +++++++++--------- .../video/rockchip/transmitter/dp_anx6345.c | 560 +++++++++-- .../video/rockchip/transmitter/dpcd_edid.h | 134 +++ 3 files changed, 1044 insertions(+), 582 deletions(-) create mode 100644 drivers/video/rockchip/transmitter/dpcd_edid.h diff --git a/drivers/video/rockchip/transmitter/anx6345.h b/drivers/video/rockchip/transmitter/anx6345.h index c152d7e4268a..11f3599ce36d 100644 --- a/drivers/video/rockchip/transmitter/anx6345.h +++ b/drivers/video/rockchip/transmitter/anx6345.h @@ -13,6 +13,10 @@ #define DP_TX_PORT0_ADDR 0x70 #define HDMI_TX_PORT0_ADDR 0x72 +#define DP_TIMEOUT_LOOP_CNT 100 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 5 + /***************************************************************/ // DEV_ADDR = 0x7A or 0x7B , MIPI Rx Registers #define MIPI_ANALOG_PWD_CTRL0 0x00 @@ -45,56 +49,56 @@ /***************************************************************/ // DEV_ADDR = 0x70 or 0x78 , Displayport mode and HDCP registers -#define SP_TX_HDCP_STATUS 0x00 -#define SP_TX_HDCP_AUTH_PASS 0x02//bit position - -#define SP_TX_HDCP_CONTROL_0_REG 0x01 -#define SP_TX_HDCP_CONTROL_0_STORE_AN 0x80//bit position -#define SP_TX_HDCP_CONTROL_0_RX_REPEATER 0x40//bit position -#define SP_TX_HDCP_CONTROL_0_RE_AUTH 0x20//bit position -#define SP_TX_HDCP_CONTROL_0_SW_AUTH_OK 0x10//bit position -#define SP_TX_HDCP_CONTROL_0_HARD_AUTH_EN 0x08//bit position -#define SP_TX_HDCP_CONTROL_0_HDCP_ENC_EN 0x04//bit position -#define SP_TX_HDCP_CONTROL_0_BKSV_SRM_PASS 0x02//bit position -#define SP_TX_HDCP_CONTROL_0_KSVLIST_VLD 0x01//bit position - - -#define SP_TX_HDCP_CONTROL_1_REG 0x02 -#define SP_TX_HDCP_CONTROL_1_DDC_NO_STOP 0x20//bit position -#define SP_TX_HDCP_CONTROL_1_DDC_NO_ACK 0x10//bit position -#define SP_TX_HDCP_CONTROL_1_EDDC_NO_ACK 0x08//bit position -//#define SP_TX_HDCP_CONTROL_1_HDCP_EMB_SCREEN_EN 0x04//bit position -#define SP_TX_HDCP_CONTROL_1_RCV_11_EN 0x02//bit position -#define SP_TX_HDCP_CONTROL_1_HDCP_11_EN 0x01//bit position - -#define SP_TX_HDCP_LINK_CHK_FRAME_NUM 0x03 -#define SP_TX_HDCP_CONTROL_2_REG 0x04 - -#define SP_TX_HDCP_AKSV0 0x05 -#define SP_TX_HDCP_AKSV1 0x06 -#define SP_TX_HDCP_AKSV2 0x07 -#define SP_TX_HDCP_AKSV3 0x08 -#define SP_TX_HDCP_AKSV4 0x09 +#define HDCP_STATUS 0x00 +#define HDCP_AUTH_PASS 0x02//bit position + +#define HDCP_CONTROL_0_REG 0x01 +#define HDCP_CONTROL_0_STORE_AN 0x80//bit position +#define HDCP_CONTROL_0_RX_REPEATER 0x40//bit position +#define HDCP_CONTROL_0_RE_AUTH 0x20//bit position +#define HDCP_CONTROL_0_SW_AUTH_OK 0x10//bit position +#define HDCP_CONTROL_0_HARD_AUTH_EN 0x08//bit position +#define HDCP_CONTROL_0_HDCP_ENC_EN 0x04//bit position +#define HDCP_CONTROL_0_BKSV_SRM_PASS 0x02//bit position +#define HDCP_CONTROL_0_KSVLIST_VLD 0x01//bit position + + +#define HDCP_CONTROL_1_REG 0x02 +#define HDCP_CONTROL_1_DDC_NO_STOP 0x20//bit position +#define HDCP_CONTROL_1_DDC_NO_ACK 0x10//bit position +#define HDCP_CONTROL_1_EDDC_NO_ACK 0x08//bit position +//#define HDCP_CONTROL_1_HDCP_EMB_SCREEN_EN 0x04//bit position +#define HDCP_CONTROL_1_RCV_11_EN 0x02//bit position +#define HDCP_CONTROL_1_HDCP_11_EN 0x01//bit position + +#define HDCP_LINK_CHK_FRAME_NUM 0x03 +#define HDCP_CONTROL_2_REG 0x04 + +#define HDCP_AKSV0 0x05 +#define HDCP_AKSV1 0x06 +#define HDCP_AKSV2 0x07 +#define HDCP_AKSV3 0x08 +#define HDCP_AKSV4 0x09 //AKSV -#define SP_TX_HDCP_AN0 0x0A -#define SP_TX_HDCP_AN1 0x0B -#define SP_TX_HDCP_AN2 0x0C -#define SP_TX_HDCP_AN3 0x0D -#define SP_TX_HDCP_AN4 0x0E -#define SP_TX_HDCP_AN5 0x0F -#define SP_TX_HDCP_AN6 0x10 -#define SP_TX_HDCP_AN7 0x11 +#define HDCP_AN0 0x0A +#define HDCP_AN1 0x0B +#define HDCP_AN2 0x0C +#define HDCP_AN3 0x0D +#define HDCP_AN4 0x0E +#define HDCP_AN5 0x0F +#define HDCP_AN6 0x10 +#define HDCP_AN7 0x11 //BKSV -#define SP_TX_HDCP_BKSV0 0x12 -#define SP_TX_HDCP_BKSV1 0x13 -#define SP_TX_HDCP_BKSV2 0x14 -#define SP_TX_HDCP_BKSV3 0x15 -#define SP_TX_HDCP_BKSV4 0x16 +#define HDCP_BKSV0 0x12 +#define HDCP_BKSV1 0x13 +#define HDCP_BKSV2 0x14 +#define HDCP_BKSV3 0x15 +#define HDCP_BKSV4 0x16 -#define SP_TX_HDCP_R0_L 0x17 -#define SP_TX_HDCP_R0_H 0x18 +#define HDCP_R0_L 0x17 +#define HDCP_R0_H 0x18 #define M_VID_0 0xC0 #define M_VID_1 0xC1 @@ -103,67 +107,67 @@ #define N_VID_1 0xC4 #define N_VID_2 0xC5 -#define SP_TX_HDCP_R0_WAIT_Timer 0x40 +#define HDCP_R0_WAIT_Timer 0x40 -#define SP_TX_SYS_CTRL1_REG 0x80 -//#define SP_TX_SYS_CTRL1_PD_IO 0x80 // bit position -//#define SP_TX_SYS_CTRL1_PD_VID 0x40 // bit position -//#define SP_TX_SYS_CTRL1_PD_LINK 0x20 // bit position -//#define SP_TX_SYS_CTRL1_PD_TOTAL 0x10 // bit position -//#define SP_TX_SYS_CTRL1_MODE_SEL 0x08 // bit position -#define SP_TX_SYS_CTRL1_DET_STA 0x04 // bit position -#define SP_TX_SYS_CTRL1_FORCE_DET 0x02 // bit position -#define SP_TX_SYS_CTRL1_DET_CTRL 0x01 // bit position +#define SYS_CTRL1_REG 0x80 +//#define SYS_CTRL1_PD_IO 0x80 // bit position +//#define SYS_CTRL1_PD_VID 0x40 // bit position +//#define SYS_CTRL1_PD_LINK 0x20 // bit position +//#define SYS_CTRL1_PD_TOTAL 0x10 // bit position +//#define SYS_CTRL1_MODE_SEL 0x08 // bit position +#define SYS_CTRL1_DET_STA 0x04 // bit position +#define SYS_CTRL1_FORCE_DET 0x02 // bit position +#define SYS_CTRL1_DET_CTRL 0x01 // bit position -#define SP_TX_SYS_CTRL2_REG 0x81 -// #define SP_TX_SYS_CTRL2_ENHANCED 0x08 //bit position -#define SP_TX_SYS_CTRL2_CHA_STA 0x04 // bit position -#define SP_TX_SYS_CTRL2_FORCE_CHA 0x02 // bit position -#define SP_TX_SYS_CTRL2_CHA_CTRL 0x01 // bit position +#define SYS_CTRL2_REG 0x81 +// #define SYS_CTRL2_ENHANCED 0x08 //bit position +#define SYS_CTRL2_CHA_STA 0x04 // bit position +#define SYS_CTRL2_FORCE_CHA 0x02 // bit position +#define SYS_CTRL2_CHA_CTRL 0x01 // bit position -#define SP_TX_SYS_CTRL3_REG 0x82 -#define SP_TX_SYS_CTRL3_HPD_STATUS 0x40 // bit position -#define SP_TX_SYS_CTRL3_F_HPD 0x20 // bit position -#define SP_TX_SYS_CTRL3_HPD_CTRL 0x10 // bit position -#define SP_TX_SYS_CTRL3_STRM_VALID 0x04 // bit position -#define SP_TX_SYS_CTRL3_F_VALID 0x02 // bit position -#define SP_TX_SYS_CTRL3_VALID_CTRL 0x01 // bit position +#define SYS_CTRL3_REG 0x82 +#define SYS_CTRL3_HPD_STATUS 0x40 // bit position +#define SYS_CTRL3_F_HPD 0x20 // bit position +#define SYS_CTRL3_HPD_CTRL 0x10 // bit position +#define SYS_CTRL3_STRM_VALID 0x04 // bit position +#define SYS_CTRL3_F_VALID 0x02 // bit position +#define SYS_CTRL3_VALID_CTRL 0x01 // bit position -#define SP_TX_SYS_CTRL4_REG 0x83 -#define SP_TX_SYS_CTRL4_ENHANCED 0x08//bit position +#define SYS_CTRL4_REG 0x83 +#define SYS_CTRL4_ENHANCED 0x08//bit position -#define SP_TX_VID_CTRL 0x84 +#define VID_CTRL 0x84 -#define SP_TX_AUD_CTRL 0x87 -#define SP_TX_AUD_CTRL_AUD_EN 0x01 +#define AUD_CTRL 0x87 +#define AUD_CTRL_AUD_EN 0x01 -#define SP_TX_PKT_EN_REG 0x90 -#define SP_TX_PKT_AUD_UP 0x80 // bit position -#define SP_TX_PKT_AVI_UD 0x40 // bit position -#define SP_TX_PKT_MPEG_UD 0x20 // bit position -#define SP_TX_PKT_SPD_UD 0x10 // bit position -#define SP_TX_PKT_AUD_EN 0x08 // bit position= -#define SP_TX_PKT_AVI_EN 0x04 // bit position -#define SP_TX_PKT_MPEG_EN 0x02 // bit position -#define SP_TX_PKT_SPD_EN 0x01 // bit position +#define PKT_EN_REG 0x90 +#define PKT_AUD_UP 0x80 // bit position +#define PKT_AVI_UD 0x40 // bit position +#define PKT_MPEG_UD 0x20 // bit position +#define PKT_SPD_UD 0x10 // bit position +#define PKT_AUD_EN 0x08 // bit position= +#define PKT_AVI_EN 0x04 // bit position +#define PKT_MPEG_EN 0x02 // bit position +#define PKT_SPD_EN 0x01 // bit position -#define SP_TX_HDCP_CTRL 0x92 +#define HDCP_CTRL 0x92 -#define SP_TX_LINK_BW_SET_REG 0xA0 -#define SP_TX_LANE_COUNT_SET_REG 0xA1 +#define LINK_BW_SET_REG 0xA0 +#define LANE_COUNT_SET_REG 0xA1 -#define SP_TX_TRAINING_PTN_SET_REG 0xA2 -#define SP_TX_SCRAMBLE_DISABLE 0x20//bit 5 +#define TRAINING_PTN_SET_REG 0xA2 +#define SCRAMBLE_DISABLE 0x20//bit 5 -#define SP_TX_TRAINING_LANE0_SET_REG 0xA3 -#define SP_TX_TRAINING_LANE0_SET_MAX_PRE_REACH 0x20 // bit position -#define SP_TX_TRAINING_LANE0_SET_MAX_DRIVE_REACH 0x04 // bit position +#define TRAINING_LANE0_SET_REG 0xA3 +#define TRAINING_LANE0_SET_MAX_PRE_REACH 0x20 // bit position +#define TRAINING_LANE0_SET_MAX_DRIVE_REACH 0x04 // bit position -#define SP_TX_TRAINING_LANE1_SET_REG 0xA4 +#define TRAINING_LANE1_SET_REG 0xA4 #define SSC_CTRL_REG1 0xA7 @@ -171,112 +175,112 @@ #define MODULATION_FREQ 0x01//bit 0 -#define SP_TX_LINK_TRAINING_CTRL_REG 0xA8 -#define SP_TX_LINK_TRAINING_CTRL_EN 0x01 // bit position +#define LINK_TRAINING_CTRL_REG 0xA8 +#define LINK_TRAINING_CTRL_EN 0x01 // bit position -#define SP_TX_DEBUG_REG1 0xB0 -#define SP_TX_DEBUG_HPD_POLLING_DET 0x40//bit position -#define SP_TX_DEBUG_HPD_POLLING_EN 0x20//bit position -#define SP_TX_DEBUG_PLL_LOCK 0x10//bit position +#define DEBUG_REG1 0xB0 +#define DEBUG_HPD_POLLING_DET 0x40//bit position +#define DEBUG_HPD_POLLING_EN 0x20//bit position +#define DEBUG_PLL_LOCK 0x10//bit position -#define SP_TX_LINK_DEBUG_REG 0xB8 -#define SP_TX_LINK_DEBUG_INSERT_ER 0x02 // bit position -#define SP_TX_LINK_DEBUG_PRBS31_EN 0x01 // bit position +#define LINK_DEBUG_REG 0xB8 +#define LINK_DEBUG_INSERT_ER 0x02 // bit position +#define LINK_DEBUG_PRBS31_EN 0x01 // bit position -#define SP_TX_SINK_COUNT_REG 0xB9 +#define SINK_COUNT_REG 0xB9 -#define SP_TX_LINK_STATUS_REG1 0xBB +#define LINK_STATUS_REG1 0xBB -#define SP_TX_SINK_STATUS_REG 0xBE -#define SP_TX_SINK_STATUS_SINK_STATUS_1 0x02 // bit position -#define SP_TX_SINK_STATUS_SINK_STATUS_0 0x01 // bit position +#define SINK_STATUS_REG 0xBE +#define SINK_STATUS_SINK_STATUS_1 0x02 // bit position +#define SINK_STATUS_SINK_STATUS_0 0x01 // bit position -//#define SP_TX_LINK_TEST_COUNT 0xC0 +//#define LINK_TEST_COUNT 0xC0 -#define SP_TX_PLL_CTRL_REG 0xC7 -#define SP_TX_PLL_CTRL_PLL_PD 0x80 // bit position -#define SP_TX_PLL_CTRL_PLL_RESET 0x40 // bit position -//#define SP_TX_PLL_CTRL_CPREG_BLEED 0x08 // bit position +#define PLL_CTRL_REG 0xC7 +#define PLL_CTRL_PLL_PD 0x80 // bit position +#define PLL_CTRL_PLL_RESET 0x40 // bit position +//#define PLL_CTRL_CPREG_BLEED 0x08 // bit position -#define SP_TX_ANALOG_POWER_DOWN_REG 0xC8 -#define SP_TX_ANALOG_POWER_DOWN_MACRO_PD 0x20 // bit position -#define SP_TX_ANALOG_POWER_DOWN_AUX_PD 0x10 // bit position -//#define SP_TX_ANALOG_POWER_DOWN_CH3_PD 0x08 // bit position -//#define SP_TX_ANALOG_POWER_DOWN_CH2_PD 0x04 // bit position -#define SP_TX_ANALOG_POWER_DOWN_CH1_PD 0x02 // bit position -#define SP_TX_ANALOG_POWER_DOWN_CH0_PD 0x01 // bit position +#define ANALOG_POWER_DOWN_REG 0xC8 +#define ANALOG_POWER_DOWN_MACRO_PD 0x20 // bit position +#define ANALOG_POWER_DOWN_AUX_PD 0x10 // bit position +//#define ANALOG_POWER_DOWN_CH3_PD 0x08 // bit position +//#define ANALOG_POWER_DOWN_CH2_PD 0x04 // bit position +#define ANALOG_POWER_DOWN_CH1_PD 0x02 // bit position +#define ANALOG_POWER_DOWN_CH0_PD 0x01 // bit position -#define SP_TX_ANALOG_TEST_REG 0xC9 -#define SP_TX_ANALOG_TEST_MACRO_RST 0x20 // bit position -#define SP_TX_ANALOG_TEST_PLL_TEST 0x10 // bit position -#define SP_TX_ANALOG_TEST_CH3_TEST 0x08 // bit position -#define SP_TX_ANALOG_TEST_CH2_TEST 0x04 // bit position -#define SP_TX_ANALOG_TEST_CH1_TEST 0x02 // bit position -#define SP_TX_ANALOG_TEST_CH0_TEST 0x01 // bit position +#define ANALOG_TEST_REG 0xC9 +#define ANALOG_TEST_MACRO_RST 0x20 // bit position +#define ANALOG_TEST_PLL_TEST 0x10 // bit position +#define ANALOG_TEST_CH3_TEST 0x08 // bit position +#define ANALOG_TEST_CH2_TEST 0x04 // bit position +#define ANALOG_TEST_CH1_TEST 0x02 // bit position +#define ANALOG_TEST_CH0_TEST 0x01 // bit position -#define SP_TX_GNS_CTRL_REG 0xCD +#define GNS_CTRL_REG 0xCD #define SP_EQ_LOOP_CNT 0x40//bit position -#define SP_TX_VIDEO_MAP_CTRL 0x02 // bit position -#define SP_TX_RS_CTRL 0x01 // bit position +#define VIDEO_MAP_CTRL 0x02 // bit position +#define RS_CTRL 0x01 // bit position -#define SP_TX_DOWN_SPREADING_CTRL1 0xD0 //guochuncheng -#define SP_TX_DOWN_SPREADING_CTRL2 0xD1 -#define SP_TX_DOWN_SPREADING_CTRL3 0xD2 -#define SP_TX_SSC_D_CTRL 0x40 //bit position -#define SP_TX_FS_CTRL_TH_CTRL 0x20 //bit position +#define DOWN_SPREADING_CTRL1 0xD0 //guochuncheng +#define DOWN_SPREADING_CTRL2 0xD1 +#define DOWN_SPREADING_CTRL3 0xD2 +#define SSC_D_CTRL 0x40 //bit position +#define FS_CTRL_TH_CTRL 0x20 //bit position -#define SP_TX_M_CALCU_CTRL 0xD9 +#define M_CALCU_CTRL 0xD9 #define M_GEN_CLK_SEL 0x01//bit 0 -#define SP_TX_EXTRA_ADDR_REG 0xCE -#define SP_TX_I2C_STRETCH_CTRL_REG 0xDB -#define SP_TX_AUX_STATUS 0xE0 -#define SP_TX_DEFER_CTRL_REG 0xE2 +#define EXTRA_ADDR_REG 0xCE +#define I2C_STRETCH_CTRL_REG 0xDB +#define AUX_STATUS 0xE0 +#define DEFER_CTRL_REG 0xE2 #define SP_TXL_DEFER_CTRL_EN 0x80 // bit position -#define SP_TX_BUF_DATA_COUNT_REG 0xE4 -#define SP_TX_AUX_CTRL_REG 0xE5 -#define SP_TX_MOT_BIT 0x04//bit 2 - -#define SP_TX_AUX_ADDR_7_0_REG 0xE6 -#define SP_TX_AUX_ADDR_15_8_REG 0xE7 -#define SP_TX_AUX_ADDR_19_16_REG 0xE8 - -#define SP_TX_AUX_CTRL_REG2 0xE9 -#define SP_TX_ADDR_ONLY_BIT 0x02//bit 1 - -#define SP_TX_BUF_DATA_0_REG 0xf0 -#define SP_TX_BUF_DATA_1_REG 0xf1 -#define SP_TX_BUF_DATA_2_REG 0xf2 -#define SP_TX_BUF_DATA_3_REG 0xf3 -#define SP_TX_BUF_DATA_4_REG 0xf4 -#define SP_TX_BUF_DATA_5_REG 0xf5 -#define SP_TX_BUF_DATA_6_REG 0xf6 -#define SP_TX_BUF_DATA_7_REG 0xf7 -#define SP_TX_BUF_DATA_8_REG 0xf8 -#define SP_TX_BUF_DATA_9_REG 0xf9 -#define SP_TX_BUF_DATA_10_REG 0xfa -#define SP_TX_BUF_DATA_11_REG 0xfb -#define SP_TX_BUF_DATA_12_REG 0xfc -#define SP_TX_BUF_DATA_13_REG 0xfd -#define SP_TX_BUF_DATA_14_REG 0xfe -#define SP_TX_BUF_DATA_15_REG 0xff +#define BUF_DATA_COUNT_REG 0xE4 +#define AUX_CTRL_REG 0xE5 +#define MOT_BIT 0x04//bit 2 + +#define AUX_ADDR_7_0_REG 0xE6 +#define AUX_ADDR_15_8_REG 0xE7 +#define AUX_ADDR_19_16_REG 0xE8 + +#define AUX_CTRL_REG2 0xE9 +#define ADDR_ONLY_BIT 0x02//bit 1 + +#define BUF_DATA_0_REG 0xf0 +#define BUF_DATA_1_REG 0xf1 +#define BUF_DATA_2_REG 0xf2 +#define BUF_DATA_3_REG 0xf3 +#define BUF_DATA_4_REG 0xf4 +#define BUF_DATA_5_REG 0xf5 +#define BUF_DATA_6_REG 0xf6 +#define BUF_DATA_7_REG 0xf7 +#define BUF_DATA_8_REG 0xf8 +#define BUF_DATA_9_REG 0xf9 +#define BUF_DATA_10_REG 0xfa +#define BUF_DATA_11_REG 0xfb +#define BUF_DATA_12_REG 0xfc +#define BUF_DATA_13_REG 0xfd +#define BUF_DATA_14_REG 0xfe +#define BUF_DATA_15_REG 0xff //End for Address 0x70 or 0x78 /***************************************************************/ // DEV_ADDR = 0x72 or 0x76, System control registers -#define SP_TX_VND_IDL_REG 0x00 -#define SP_TX_VND_IDH_REG 0x01 -#define SP_TX_DEV_IDL_REG 0x02 -#define SP_TX_DEV_IDH_REG 0x03 -#define SP_TX_DEV_REV_REG 0x04 +#define VND_IDL_REG 0x00 +#define VND_IDH_REG 0x01 +#define DEV_IDL_REG 0x02 +#define DEV_IDH_REG 0x03 +#define DEV_REV_REG 0x04 #define SP_POWERD_CTRL_REG 0x05 #define SP_POWERD_REGISTER_REG 0x80// bit position @@ -288,100 +292,100 @@ #define SP_POWERD_TOTAL_REG 0x02// bit position #define SP_MODE_SEL_REG 0x01// bit position -#define SP_TX_RST_CTRL_REG 0x06 -#define SP_TX_RST_MISC_REG 0x80 // bit position -#define SP_TX_RST_VIDCAP_REG 0x40 // bit position -#define SP_TX_RST_VIDFIF_REG 0x20 // bit position -#define SP_TX_RST_AUDFIF_REG 0x10 // bit position -#define SP_TX_RST_AUDCAP_REG 0x08 // bit position -#define SP_TX_RST_HDCP_REG 0x04 // bit position -#define SP_TX_RST_SW_RST 0x02 // bit position -#define SP_TX_RST_HW_RST 0x01 // bit position - -#define SP_TX_RST_CTRL2_REG 0x07 -#define SP_TX_RST_SSC 0x80//bit position -#define SP_TX_AC_MODE 0x40//bit position -//#define SP_TX_DDC_RST 0x10//bit position -//#define SP_TX_TMDS_BIST_RST 0x08//bit position -#define SP_TX_AUX_RST 0x04//bit position -#define SP_TX_SERDES_FIFO_RST 0x02//bit position -#define SP_TX_I2C_REG_RST 0x01//bit position - - -#define SP_TX_VID_CTRL1_REG 0x08 -#define SP_TX_VID_CTRL1_VID_EN 0x80 // bit position -#define SP_TX_VID_CTRL1_VID_MUTE 0x40 // bit position -#define SP_TX_VID_CTRL1_DE_GEN 0x20 // bit position -#define SP_TX_VID_CTRL1_DEMUX 0x10 // bit position -#define SP_TX_VID_CTRL1_IN_BIT 0x04 // bit position -#define SP_TX_VID_CTRL1_DDRCTRL 0x02 // bit position -#define SP_TX_VID_CTRL1_EDGE 0x01 // bit position - -#define SP_TX_VID_CTRL2_REG 0x09 -#define SP_TX_VID_CTRL1_YCBIT_SEL 0x04 // bit position - -#define SP_TX_VID_CTRL3_REG 0x0A - -#define SP_TX_VID_CTRL4_REG 0x0B -#define SP_TX_VID_CTRL4_E_SYNC_EN 0x80 //bit position -#define SP_TX_VID_CTRL4_EX_E_SYNC 0x40 // bit position -#define SP_TX_VID_CTRL4_BIST 0x08 // bit position -#define SP_TX_VID_CTRL4_BIST_WIDTH 0x04 // bit position - -#define SP_TX_VID_CTRL5_REG 0x0C - -#define SP_TX_VID_CTRL6_REG 0x0D -#define SP_TX_VID_UPSAMPLE 0x02//bit position - -#define SP_TX_VID_CTRL7_REG 0x0E -#define SP_TX_VID_CTRL8_REG 0x0F -#define SP_TX_VID_CTRL9_REG 0x10 - -#define SP_TX_VID_CTRL10_REG 0x11 -#define SP_TX_VID_CTRL10_INV_F 0x08 // bit position -#define SP_TX_VID_CTRL10_I_SCAN 0x04 // bit position -#define SP_TX_VID_CTRL10_VSYNC_POL 0x02 // bit position -#define SP_TX_VID_CTRL10_HSYNC_POL 0x01 // bit position - -#define SP_TX_TOTAL_LINEL_REG 0x12 -#define SP_TX_TOTAL_LINEH_REG 0x13 -#define SP_TX_ACT_LINEL_REG 0x14 -#define SP_TX_ACT_LINEH_REG 0x15 -#define SP_TX_VF_PORCH_REG 0x16 -#define SP_TX_VSYNC_CFG_REG 0x17 -#define SP_TX_VB_PORCH_REG 0x18 -#define SP_TX_TOTAL_PIXELL_REG 0x19 -#define SP_TX_TOTAL_PIXELH_REG 0x1A -#define SP_TX_ACT_PIXELL_REG 0x1B -#define SP_TX_ACT_PIXELH_REG 0x1C -#define SP_TX_HF_PORCHL_REG 0x1D -#define SP_TX_HF_PORCHH_REG 0x1E -#define SP_TX_HSYNC_CFGL_REG 0x1F -#define SP_TX_HSYNC_CFGH_REG 0x20 -#define SP_TX_HB_PORCHL_REG 0x21 -#define SP_TX_HB_PORCHH_REG 0x22 - -#define SP_TX_VID_STATUS 0x23 - -#define SP_TX_TOTAL_LINE_STA_L 0x24 -#define SP_TX_TOTAL_LINE_STA_H 0x25 -#define SP_TX_ACT_LINE_STA_L 0x26 -#define SP_TX_ACT_LINE_STA_H 0x27 -#define SP_TX_V_F_PORCH_STA 0x28 -#define SP_TX_V_SYNC_STA 0x29 -#define SP_TX_V_B_PORCH_STA 0x2A -#define SP_TX_TOTAL_PIXEL_STA_L 0x2B -#define SP_TX_TOTAL_PIXEL_STA_H 0x2C -#define SP_TX_ACT_PIXEL_STA_L 0x2D -#define SP_TX_ACT_PIXEL_STA_H 0x2E -#define SP_TX_H_F_PORCH_STA_L 0x2F -#define SP_TX_H_F_PORCH_STA_H 0x30 -#define SP_TX_H_SYNC_STA_L 0x31 -#define SP_TX_H_SYNC_STA_H 0x32 -#define SP_TX_H_B_PORCH_STA_L 0x33 -#define SP_TX_H_B_PORCH_STA_H 0x34 - -#define SP_TX_Video_Interface_BIST 0x35 +#define RST_CTRL_REG 0x06 +#define RST_MISC_REG 0x80 // bit position +#define RST_VIDCAP_REG 0x40 // bit position +#define RST_VIDFIF_REG 0x20 // bit position +#define RST_AUDFIF_REG 0x10 // bit position +#define RST_AUDCAP_REG 0x08 // bit position +#define RST_HDCP_REG 0x04 // bit position +#define RST_SW_RST 0x02 // bit position +#define RST_HW_RST 0x01 // bit position + +#define RST_CTRL2_REG 0x07 +#define RST_SSC 0x80//bit position +#define AC_MODE 0x40//bit position +//#define DDC_RST 0x10//bit position +//#define TMDS_BIST_RST 0x08//bit position +#define AUX_RST 0x04//bit position +#define SERDES_FIFO_RST 0x02//bit position +#define I2C_REG_RST 0x01//bit position + + +#define VID_CTRL1_REG 0x08 +#define VID_CTRL1_VID_EN 0x80 // bit position +#define VID_CTRL1_VID_MUTE 0x40 // bit position +#define VID_CTRL1_DE_GEN 0x20 // bit position +#define VID_CTRL1_DEMUX 0x10 // bit position +#define VID_CTRL1_IN_BIT 0x04 // bit position +#define VID_CTRL1_DDRCTRL 0x02 // bit position +#define VID_CTRL1_EDGE 0x01 // bit position + +#define VID_CTRL2_REG 0x09 +#define VID_CTRL1_YCBIT_SEL 0x04 // bit position + +#define VID_CTRL3_REG 0x0A + +#define VID_CTRL4_REG 0x0B +#define VID_CTRL4_E_SYNC_EN 0x80 //bit position +#define VID_CTRL4_EX_E_SYNC 0x40 // bit position +#define VID_CTRL4_BIST 0x08 // bit position +#define VID_CTRL4_BIST_WIDTH 0x04 // bit position + +#define VID_CTRL5_REG 0x0C + +#define VID_CTRL6_REG 0x0D +#define VID_UPSAMPLE 0x02//bit position + +#define VID_CTRL7_REG 0x0E +#define VID_CTRL8_REG 0x0F +#define VID_CTRL9_REG 0x10 + +#define VID_CTRL10_REG 0x11 +#define VID_CTRL10_INV_F 0x08 // bit position +#define VID_CTRL10_I_SCAN 0x04 // bit position +#define VID_CTRL10_VSYNC_POL 0x02 // bit position +#define VID_CTRL10_HSYNC_POL 0x01 // bit position + +#define TOTAL_LINEL_REG 0x12 +#define TOTAL_LINEH_REG 0x13 +#define ACT_LINEL_REG 0x14 +#define ACT_LINEH_REG 0x15 +#define VF_PORCH_REG 0x16 +#define VSYNC_CFG_REG 0x17 +#define VB_PORCH_REG 0x18 +#define TOTAL_PIXELL_REG 0x19 +#define TOTAL_PIXELH_REG 0x1A +#define ACT_PIXELL_REG 0x1B +#define ACT_PIXELH_REG 0x1C +#define HF_PORCHL_REG 0x1D +#define HF_PORCHH_REG 0x1E +#define HSYNC_CFGL_REG 0x1F +#define HSYNC_CFGH_REG 0x20 +#define HB_PORCHL_REG 0x21 +#define HB_PORCHH_REG 0x22 + +#define VID_STATUS 0x23 + +#define TOTAL_LINE_STA_L 0x24 +#define TOTAL_LINE_STA_H 0x25 +#define ACT_LINE_STA_L 0x26 +#define ACT_LINE_STA_H 0x27 +#define V_F_PORCH_STA 0x28 +#define V_SYNC_STA 0x29 +#define V_B_PORCH_STA 0x2A +#define TOTAL_PIXEL_STA_L 0x2B +#define TOTAL_PIXEL_STA_H 0x2C +#define ACT_PIXEL_STA_L 0x2D +#define ACT_PIXEL_STA_H 0x2E +#define H_F_PORCH_STA_L 0x2F +#define H_F_PORCH_STA_H 0x30 +#define H_SYNC_STA_L 0x31 +#define H_SYNC_STA_H 0x32 +#define H_B_PORCH_STA_L 0x33 +#define H_B_PORCH_STA_H 0x34 + +#define Video_Interface_BIST 0x35 #define SPDIF_AUDIO_CTRL0 0x36 #define SPDIF_AUDIO_CTRL0_SPDIF_IN 0x80 // bit position @@ -401,157 +405,157 @@ //#define AUDIO_BIST_CHANNEL_STATUS4 0xd3 //#define AUDIO_BIST_CHANNEL_STATUS5 0xd4 -#define SP_TX_VIDEO_BIT_CTRL_0_REG 0x40 -#define SP_TX_VIDEO_BIT_CTRL_1_REG 0x41 -#define SP_TX_VIDEO_BIT_CTRL_2_REG 0x42 -#define SP_TX_VIDEO_BIT_CTRL_3_REG 0x43 -#define SP_TX_VIDEO_BIT_CTRL_4_REG 0x44 -#define SP_TX_VIDEO_BIT_CTRL_5_REG 0x45 -#define SP_TX_VIDEO_BIT_CTRL_6_REG 0x46 -#define SP_TX_VIDEO_BIT_CTRL_7_REG 0x47 -#define SP_TX_VIDEO_BIT_CTRL_8_REG 0x48 -#define SP_TX_VIDEO_BIT_CTRL_9_REG 0x49 -#define SP_TX_VIDEO_BIT_CTRL_10_REG 0x4a -#define SP_TX_VIDEO_BIT_CTRL_11_REG 0x4b -#define SP_TX_VIDEO_BIT_CTRL_12_REG 0x4c -#define SP_TX_VIDEO_BIT_CTRL_13_REG 0x4d -#define SP_TX_VIDEO_BIT_CTRL_14_REG 0x4e -#define SP_TX_VIDEO_BIT_CTRL_15_REG 0x4f -#define SP_TX_VIDEO_BIT_CTRL_16_REG 0x50 -#define SP_TX_VIDEO_BIT_CTRL_17_REG 0x51 -#define SP_TX_VIDEO_BIT_CTRL_18_REG 0x52 -#define SP_TX_VIDEO_BIT_CTRL_19_REG 0x53 -#define SP_TX_VIDEO_BIT_CTRL_20_REG 0x54 -#define SP_TX_VIDEO_BIT_CTRL_21_REG 0x55 -#define SP_TX_VIDEO_BIT_CTRL_22_REG 0x56 -#define SP_TX_VIDEO_BIT_CTRL_23_REG 0x57 -#define SP_TX_VIDEO_BIT_CTRL_24_REG 0x58 -#define SP_TX_VIDEO_BIT_CTRL_25_REG 0x59 -#define SP_TX_VIDEO_BIT_CTRL_26_REG 0x5a -#define SP_TX_VIDEO_BIT_CTRL_27_REG 0x5b -#define SP_TX_VIDEO_BIT_CTRL_28_REG 0x5c -#define SP_TX_VIDEO_BIT_CTRL_29_REG 0x5d -#define SP_TX_VIDEO_BIT_CTRL_30_REG 0x5e -#define SP_TX_VIDEO_BIT_CTRL_31_REG 0x5f -#define SP_TX_VIDEO_BIT_CTRL_32_REG 0x60 -#define SP_TX_VIDEO_BIT_CTRL_33_REG 0x61 -#define SP_TX_VIDEO_BIT_CTRL_34_REG 0x62 -#define SP_TX_VIDEO_BIT_CTRL_35_REG 0x63 -#define SP_TX_VIDEO_BIT_CTRL_36_REG 0x64 -#define SP_TX_VIDEO_BIT_CTRL_37_REG 0x65 -#define SP_TX_VIDEO_BIT_CTRL_38_REG 0x66 -#define SP_TX_VIDEO_BIT_CTRL_39_REG 0x67 -#define SP_TX_VIDEO_BIT_CTRL_40_REG 0x68 -#define SP_TX_VIDEO_BIT_CTRL_41_REG 0x69 -#define SP_TX_VIDEO_BIT_CTRL_42_REG 0x6a -#define SP_TX_VIDEO_BIT_CTRL_43_REG 0x6b -#define SP_TX_VIDEO_BIT_CTRL_44_REG 0x6c -#define SP_TX_VIDEO_BIT_CTRL_45_REG 0x6d -#define SP_TX_VIDEO_BIT_CTRL_46_REG 0x6e -#define SP_TX_VIDEO_BIT_CTRL_47_REG 0x6f +#define VIDEO_BIT_CTRL_0_REG 0x40 +#define VIDEO_BIT_CTRL_1_REG 0x41 +#define VIDEO_BIT_CTRL_2_REG 0x42 +#define VIDEO_BIT_CTRL_3_REG 0x43 +#define VIDEO_BIT_CTRL_4_REG 0x44 +#define VIDEO_BIT_CTRL_5_REG 0x45 +#define VIDEO_BIT_CTRL_6_REG 0x46 +#define VIDEO_BIT_CTRL_7_REG 0x47 +#define VIDEO_BIT_CTRL_8_REG 0x48 +#define VIDEO_BIT_CTRL_9_REG 0x49 +#define VIDEO_BIT_CTRL_10_REG 0x4a +#define VIDEO_BIT_CTRL_11_REG 0x4b +#define VIDEO_BIT_CTRL_12_REG 0x4c +#define VIDEO_BIT_CTRL_13_REG 0x4d +#define VIDEO_BIT_CTRL_14_REG 0x4e +#define VIDEO_BIT_CTRL_15_REG 0x4f +#define VIDEO_BIT_CTRL_16_REG 0x50 +#define VIDEO_BIT_CTRL_17_REG 0x51 +#define VIDEO_BIT_CTRL_18_REG 0x52 +#define VIDEO_BIT_CTRL_19_REG 0x53 +#define VIDEO_BIT_CTRL_20_REG 0x54 +#define VIDEO_BIT_CTRL_21_REG 0x55 +#define VIDEO_BIT_CTRL_22_REG 0x56 +#define VIDEO_BIT_CTRL_23_REG 0x57 +#define VIDEO_BIT_CTRL_24_REG 0x58 +#define VIDEO_BIT_CTRL_25_REG 0x59 +#define VIDEO_BIT_CTRL_26_REG 0x5a +#define VIDEO_BIT_CTRL_27_REG 0x5b +#define VIDEO_BIT_CTRL_28_REG 0x5c +#define VIDEO_BIT_CTRL_29_REG 0x5d +#define VIDEO_BIT_CTRL_30_REG 0x5e +#define VIDEO_BIT_CTRL_31_REG 0x5f +#define VIDEO_BIT_CTRL_32_REG 0x60 +#define VIDEO_BIT_CTRL_33_REG 0x61 +#define VIDEO_BIT_CTRL_34_REG 0x62 +#define VIDEO_BIT_CTRL_35_REG 0x63 +#define VIDEO_BIT_CTRL_36_REG 0x64 +#define VIDEO_BIT_CTRL_37_REG 0x65 +#define VIDEO_BIT_CTRL_38_REG 0x66 +#define VIDEO_BIT_CTRL_39_REG 0x67 +#define VIDEO_BIT_CTRL_40_REG 0x68 +#define VIDEO_BIT_CTRL_41_REG 0x69 +#define VIDEO_BIT_CTRL_42_REG 0x6a +#define VIDEO_BIT_CTRL_43_REG 0x6b +#define VIDEO_BIT_CTRL_44_REG 0x6c +#define VIDEO_BIT_CTRL_45_REG 0x6d +#define VIDEO_BIT_CTRL_46_REG 0x6e +#define VIDEO_BIT_CTRL_47_REG 0x6f //AVI info frame -#define SP_TX_AVI_TYPE 0x70 -#define SP_TX_AVI_VER 0x71 -#define SP_TX_AVI_LEN 0x72 -#define SP_TX_AVI_DB0 0x73 -#define SP_TX_AVI_DB1 0x74 -#define SP_TX_AVI_DB2 0x75 -#define SP_TX_AVI_DB3 0x76 -#define SP_TX_AVI_DB4 0x77 -#define SP_TX_AVI_DB5 0x78 -#define SP_TX_AVI_DB6 0x79 -#define SP_TX_AVI_DB7 0x7A -#define SP_TX_AVI_DB8 0x7B -#define SP_TX_AVI_DB9 0x7C -#define SP_TX_AVI_DB10 0x7D -#define SP_TX_AVI_DB11 0x7E -#define SP_TX_AVI_DB12 0x7F -#define SP_TX_AVI_DB13 0x80 -#define SP_TX_AVI_DB14 0x81 -#define SP_TX_AVI_DB15 0x82 +#define AVI_TYPE 0x70 +#define AVI_VER 0x71 +#define AVI_LEN 0x72 +#define AVI_DB0 0x73 +#define AVI_DB1 0x74 +#define AVI_DB2 0x75 +#define AVI_DB3 0x76 +#define AVI_DB4 0x77 +#define AVI_DB5 0x78 +#define AVI_DB6 0x79 +#define AVI_DB7 0x7A +#define AVI_DB8 0x7B +#define AVI_DB9 0x7C +#define AVI_DB10 0x7D +#define AVI_DB11 0x7E +#define AVI_DB12 0x7F +#define AVI_DB13 0x80 +#define AVI_DB14 0x81 +#define AVI_DB15 0x82 //Audio info frame -#define SP_TX_AUD_TYPE 0x83 -#define SP_TX_AUD_VER 0x84 -#define SP_TX_AUD_LEN 0x85 -#define SP_TX_AUD_DB0 0x86 -#define SP_TX_AUD_DB1 0x87 -#define SP_TX_AUD_DB2 0x88 -#define SP_TX_AUD_DB3 0x89 -#define SP_TX_AUD_DB4 0x8A -#define SP_TX_AUD_DB5 0x8B -#define SP_TX_AUD_DB6 0x8C -#define SP_TX_AUD_DB7 0x8D -#define SP_TX_AUD_DB8 0x8E -#define SP_TX_AUD_DB9 0x8F -#define SP_TX_AUD_DB10 0x90 +#define AUD_TYPE 0x83 +#define AUD_VER 0x84 +#define AUD_LEN 0x85 +#define AUD_DB0 0x86 +#define AUD_DB1 0x87 +#define AUD_DB2 0x88 +#define AUD_DB3 0x89 +#define AUD_DB4 0x8A +#define AUD_DB5 0x8B +#define AUD_DB6 0x8C +#define AUD_DB7 0x8D +#define AUD_DB8 0x8E +#define AUD_DB9 0x8F +#define AUD_DB10 0x90 //SPD info frame -#define SP_TX_SPD_TYPE 0x91 -#define SP_TX_SPD_VER 0x92 -#define SP_TX_SPD_LEN 0x93 -#define SP_TX_SPD_DATA0 0x94 -#define SP_TX_SPD_DATA1 0x95 -#define SP_TX_SPD_DATA2 0x96 -#define SP_TX_SPD_DATA3 0x97 -#define SP_TX_SPD_DATA4 0x98 -#define SP_TX_SPD_DATA5 0x99 -#define SP_TX_SPD_DATA6 0x9A -#define SP_TX_SPD_DATA7 0x9B -#define SP_TX_SPD_DATA8 0x9C -#define SP_TX_SPD_DATA9 0x9D -#define SP_TX_SPD_DATA10 0x9E -#define SP_TX_SPD_DATA11 0x9F -#define SP_TX_SPD_DATA12 0xA0 -#define SP_TX_SPD_DATA13 0xA1 -#define SP_TX_SPD_DATA14 0xA2 -#define SP_TX_SPD_DATA15 0xA3 -#define SP_TX_SPD_DATA16 0xA4 -#define SP_TX_SPD_DATA17 0xA5 -#define SP_TX_SPD_DATA18 0xA6 -#define SP_TX_SPD_DATA19 0xA7 -#define SP_TX_SPD_DATA20 0xA8 -#define SP_TX_SPD_DATA21 0xA9 -#define SP_TX_SPD_DATA22 0xAA -#define SP_TX_SPD_DATA23 0xAB -#define SP_TX_SPD_DATA24 0xAC -#define SP_TX_SPD_DATA25 0xAD -#define SP_TX_SPD_DATA26 0xAE -#define SP_TX_SPD_DATA27 0xAF +#define SPD_TYPE 0x91 +#define SPD_VER 0x92 +#define SPD_LEN 0x93 +#define SPD_DATA0 0x94 +#define SPD_DATA1 0x95 +#define SPD_DATA2 0x96 +#define SPD_DATA3 0x97 +#define SPD_DATA4 0x98 +#define SPD_DATA5 0x99 +#define SPD_DATA6 0x9A +#define SPD_DATA7 0x9B +#define SPD_DATA8 0x9C +#define SPD_DATA9 0x9D +#define SPD_DATA10 0x9E +#define SPD_DATA11 0x9F +#define SPD_DATA12 0xA0 +#define SPD_DATA13 0xA1 +#define SPD_DATA14 0xA2 +#define SPD_DATA15 0xA3 +#define SPD_DATA16 0xA4 +#define SPD_DATA17 0xA5 +#define SPD_DATA18 0xA6 +#define SPD_DATA19 0xA7 +#define SPD_DATA20 0xA8 +#define SPD_DATA21 0xA9 +#define SPD_DATA22 0xAA +#define SPD_DATA23 0xAB +#define SPD_DATA24 0xAC +#define SPD_DATA25 0xAD +#define SPD_DATA26 0xAE +#define SPD_DATA27 0xAF //Mpeg source info frame -#define SP_TX_MPEG_TYPE 0xB0 -#define SP_TX_MPEG_VER 0xB1 -#define SP_TX_MPEG_LEN 0xB2 -#define SP_TX_MPEG_DATA0 0xB3 -#define SP_TX_MPEG_DATA1 0xB4 -#define SP_TX_MPEG_DATA2 0xB5 -#define SP_TX_MPEG_DATA3 0xB6 -#define SP_TX_MPEG_DATA4 0xB7 -#define SP_TX_MPEG_DATA5 0xB8 -#define SP_TX_MPEG_DATA6 0xB9 -#define SP_TX_MPEG_DATA7 0xBA -#define SP_TX_MPEG_DATA8 0xBB -#define SP_TX_MPEG_DATA9 0xBC -#define SP_TX_MPEG_DATA10 0xBD -#define SP_TX_MPEG_DATA11 0xBE -#define SP_TX_MPEG_DATA12 0xBF -#define SP_TX_MPEG_DATA13 0xC0 -#define SP_TX_MPEG_DATA14 0xC1 -#define SP_TX_MPEG_DATA15 0xC2 -#define SP_TX_MPEG_DATA16 0xC3 -#define SP_TX_MPEG_DATA17 0xC4 -#define SP_TX_MPEG_DATA18 0xC5 -#define SP_TX_MPEG_DATA19 0xC6 -#define SP_TX_MPEG_DATA20 0xC7 -#define SP_TX_MPEG_DATA21 0xC8 -#define SP_TX_MPEG_DATA22 0xC9 -#define SP_TX_MPEG_DATA23 0xCA -#define SP_TX_MPEG_DATA24 0xCB -#define SP_TX_MPEG_DATA25 0xCC -#define SP_TX_MPEG_DATA26 0xCD -#define SP_TX_MPEG_DATA27 0xCE +#define MPEG_TYPE 0xB0 +#define MPEG_VER 0xB1 +#define MPEG_LEN 0xB2 +#define MPEG_DATA0 0xB3 +#define MPEG_DATA1 0xB4 +#define MPEG_DATA2 0xB5 +#define MPEG_DATA3 0xB6 +#define MPEG_DATA4 0xB7 +#define MPEG_DATA5 0xB8 +#define MPEG_DATA6 0xB9 +#define MPEG_DATA7 0xBA +#define MPEG_DATA8 0xBB +#define MPEG_DATA9 0xBC +#define MPEG_DATA10 0xBD +#define MPEG_DATA11 0xBE +#define MPEG_DATA12 0xBF +#define MPEG_DATA13 0xC0 +#define MPEG_DATA14 0xC1 +#define MPEG_DATA15 0xC2 +#define MPEG_DATA16 0xC3 +#define MPEG_DATA17 0xC4 +#define MPEG_DATA18 0xC5 +#define MPEG_DATA19 0xC6 +#define MPEG_DATA20 0xC7 +#define MPEG_DATA21 0xC8 +#define MPEG_DATA22 0xC9 +#define MPEG_DATA23 0xCA +#define MPEG_DATA24 0xCB +#define MPEG_DATA25 0xCC +#define MPEG_DATA26 0xCD +#define MPEG_DATA27 0xCE //#define GNSS_CTRL_REG 0xCD //#define ENABLE_SSC_FILTER 0x80//bit @@ -579,13 +583,13 @@ #define PLL_FILTER_CTRL5 0xE3 #define PLL_FILTER_CTRL6 0xE4 -#define SP_TX_I2S_CTRL 0xE6 -#define SP_TX_I2S_FMT 0xE7 -#define SP_TX_I2S_CH_Status1 0xD0 -#define SP_TX_I2S_CH_Status2 0xD1 -#define SP_TX_I2S_CH_Status3 0xD2 -#define SP_TX_I2S_CH_Status4 0xD3 -#define SP_TX_I2S_CH_Status5 0xD4 +#define I2S_CTRL 0xE6 +#define I2S_FMT 0xE7 +#define I2S_CH_Status1 0xD0 +#define I2S_CH_Status2 0xD1 +#define I2S_CH_Status3 0xD2 +#define I2S_CH_Status4 0xD3 +#define I2S_CH_Status5 0xD4 //interrupt #define SP_COMMON_INT_STATUS1 0xF1 @@ -610,74 +614,53 @@ #define SP_COMMON_INT4_HPD_CHANGE 0x04 //bit position -#define SP_TX_INT_STATUS1 0xF7 -#define SP_TX_INT_STATUS1_HPD 0x40 //bit position -#define SP_TX_INT_STATUS1_TRAINING_Finish 0x20 // bit position -#define SP_TX_INT_STATUS1_POLLING_ERR 0x10 // bit position - -#define SP_TX_INT_SINK_CHG 0x08//bit position - -//interrupt mask -#define SP_COMMON_INT_MASK1 0xF8 -#define SP_COMMON_INT_MASK2 0xF9 -#define SP_COMMON_INT_MASK3 0xFA -#define SP_COMMON_INT_MASK4 0xFB +#define INT_STATUS1 0xF7 +#define INT_STATUS1_HPD 0x40 //bit position +#define INT_STATUS1_TRAINING_Finish 0x20 // bit position +#define INT_STATUS1_POLLING_ERR 0x10 // bit position + +#define INT_SINK_CHG 0x08//bit position + + +#define AUX_CH_STA 0xe0 +#define AUX_BUSY (0x1 << 4) +#define AUX_STATUS_MASK (0xf << 0) +#define DP_AUX_RX_COMM 0xe3 +#define BUF_DATA_CTL 0xe4 +#define BUF_CLR (0x1 << 7) +#define DP_AUX_CH_CTL_1 0xe5 +#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) +#define AUX_TX_COMM_MASK (0xf << 0) +#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) +#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) +#define AUX_TX_COMM_MOT (0x1 << 2) +#define AUX_TX_COMM_WRITE (0x0 << 0) +#define AUX_TX_COMM_READ (0x1 << 0) + +#define DP_AUX_ADDR_7_0 0xe6 +#define DP_AUX_ADDR_15_8 0xe7 +#define DP_AUX_ADDR_19_16 0xe8 + +#define DP_AUX_CH_CTL_2 0xe9 +#define ADDR_ONLY (0x1 << 1) +#define AUX_EN (0x1 << 0) + +#define BUF_DATA_0 0xf0 + +#define DP_INT_STA 0xf7 +#define RPLY_RECEIV (0x1 << 1) +#define AUX_ERR (0x1 << 0) +#define SP_COMMON_INT_MASK1 0xF8 +#define SP_COMMON_INT_MASK2 0xF9 +#define SP_COMMON_INT_MASK3 0xFA +#define SP_COMMON_INT_MASK4 0xFB #define SP_INT_MASK 0xFE -#define SP_TX_INT_CTRL_REG 0xFF +#define INT_CTRL_REG 0xFF //End for dev_addr 0x72 or 0x76 /***************************************************************/ /***************************************************************/ -//DPCD regs -#define DPCD_DPCD_REV 0x00 -#define DPCD_MAX_LINK_RATE 0x01 -#define DPCD_MAX_LANE_COUNT 0x02 -#define DPCD_MAX_DOWNSPREAD 0x03 -#define DPCD_NORP 0x04 -#define DPCD_DOWNSTREAMPORT_PRESENT 0x05 - -#define DPCD_RECEIVE_PORT0_CAP_0 0x08 -#define DPCD_RECEIVE_PORT0_CAP_1 0x09 -#define DPCD_RECEIVE_PORT0_CAP_2 0x0a -#define DPCD_RECEIVE_PORT0_CAP_3 0x0b - -#define DPCD_LINK_BW_SET 0x00 -#define DPCD_LANE_COUNT_SET 0x01 -#define DPCD_TRAINING_PATTERN_SET 0x02 -#define DPCD_TRAINNIG_LANE0_SET 0x03 -#define DPCD_TRAINNIG_LANE1_SET 0x04 -#define DPCD_TRAINNIG_LANE2_SET 0x05 -#define DPCD_TRAINNIG_LANE3_SET 0x06 -#define DPCD_DOWNSPREAD_CTRL 0x07 - -#define DPCD_SINK_COUNT 0x00 -#define DPCD_DEVICE_SERVICE_IRQ_VECTOR 0x01 -#define DPCD_LANE0_1_STATUS 0x02 -#define DPCD_LANE2_3_STATUS 0x03 -#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x04 -#define DPCD_SINK_STATUS 0x05 -#define DPCD_ADJUST_REQUEST_LANE0_1 0x06 -#define DPCD_ADJUST_REQUEST_LANE2_3 0x07 -#define DPCD_TRAINING_SCORE_LANE0 0x08 -#define DPCD_TRAINING_SCORE_LANE1 0x09 -#define DPCD_TRAINING_SCORE_LANE2 0x0a -#define DPCD_TRAINING_SCORE_LANE3 0x0b - -#define DPCD_TEST_REQUEST 0x18 -#define DPCD_TEST_LINK_RATE 0x19 - -#define DPCD_TEST_LANE_COUNT 0x20 - -#define DPCD_TEST_Response 0x60 -#define TEST_ACK 0x01 -#define DPCD_TEST_EDID_Checksum_Write 0x04//bit position - -#define DPCD_TEST_EDID_Checksum 0x61 - - -#define DPCD_SPECIFIC_INTERRUPT 0x10 -#define DPCD_USER_COMM1 0x22//define for downstream HDMI Rx sense detection struct anx6345_platform_data { @@ -693,6 +676,7 @@ struct edp_anx6345 { struct i2c_client *client; struct anx6345_platform_data *pdata; struct rk_screen screen; + struct fb_monspecs specs; struct dentry *debugfs_dir; #ifdef CONFIG_HAS_EARLYSUSPEND struct early_suspend early_suspend; diff --git a/drivers/video/rockchip/transmitter/dp_anx6345.c b/drivers/video/rockchip/transmitter/dp_anx6345.c index 11fcb9eb5c01..ea148e288a38 100644 --- a/drivers/video/rockchip/transmitter/dp_anx6345.c +++ b/drivers/video/rockchip/transmitter/dp_anx6345.c @@ -13,7 +13,7 @@ #include #endif #include "anx6345.h" - +#include "dpcd_edid.h" #if defined(CONFIG_DEBUG_FS) #include #include @@ -169,8 +169,8 @@ static int get_dp_chip_id(struct i2c_client *client) { char c1,c2; int id; - anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1); - anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2); + anx6345_i2c_read_p1_reg(client,DEV_IDL_REG,&c1); + anx6345_i2c_read_p1_reg(client,DEV_IDH_REG,&c2); id = c2; return (id<<8)|c1; } @@ -624,119 +624,459 @@ static int anx980x_init(struct i2c_client *client) return 0; } -#if 1 + static int anx6345_bist_mode(struct i2c_client *client) { struct edp_anx6345 *anx6345 = i2c_get_clientdata(client); struct rk_screen *screen = &anx6345->screen; - u16 x_total ,y_total; - u32 total, act_total; + u16 x_total ,y_total, x_act; char val = 0x00; //these register are for bist mode x_total = screen->mode.left_margin + screen->mode.right_margin + screen->mode.xres + screen->mode.hsync_len; y_total = screen->mode.upper_margin + screen->mode.lower_margin + screen->mode.yres + screen->mode.vsync_len; - total = x_total * y_total; - printk("%s>>>>total:0x%08x\n",__func__, total); - act_total = screen->mode.xres * screen->mode.yres; + x_total >>= 1; + x_act = screen->mode.xres >> 1; val = y_total & 0xff; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val); + anx6345_i2c_write_p1_reg(client,TOTAL_LINEL_REG,&val); val = (y_total >> 8); - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val); + anx6345_i2c_write_p1_reg(client,TOTAL_LINEH_REG,&val); val = (screen->mode.yres & 0xff); - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val); + anx6345_i2c_write_p1_reg(client,ACT_LINEL_REG,&val); val = (screen->mode.yres >> 8); - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val); + anx6345_i2c_write_p1_reg(client,ACT_LINEH_REG,&val); val = screen->mode.lower_margin; - anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val); + anx6345_i2c_write_p1_reg(client,VF_PORCH_REG,&val); val = screen->mode.vsync_len; - anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val); + anx6345_i2c_write_p1_reg(client,VSYNC_CFG_REG,&val); val = screen->mode.upper_margin; - anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val); - val = total & 0xff; - val = 0x50; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val); - val = total >> 8; - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val); - val = (act_total & 0xff); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val); - val = (act_total >> 8); - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val); + anx6345_i2c_write_p1_reg(client,VB_PORCH_REG,&val); + val = x_total & 0xff; + anx6345_i2c_write_p1_reg(client,TOTAL_PIXELL_REG,&val); + val = x_total >> 8; + anx6345_i2c_write_p1_reg(client,TOTAL_PIXELH_REG,&val); + val = (x_act & 0xff); + anx6345_i2c_write_p1_reg(client,ACT_PIXELL_REG,&val); + val = (x_act >> 8); + anx6345_i2c_write_p1_reg(client,ACT_PIXELH_REG,&val); val = screen->mode.right_margin & 0xff; - anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val); + anx6345_i2c_write_p1_reg(client,HF_PORCHL_REG,&val); val = screen->mode.right_margin >> 8; - anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val); + anx6345_i2c_write_p1_reg(client,HF_PORCHH_REG,&val); val = screen->mode.hsync_len & 0xff; - anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val); + anx6345_i2c_write_p1_reg(client,HSYNC_CFGL_REG,&val); val = screen->mode.hsync_len >> 8; - anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val); + anx6345_i2c_write_p1_reg(client,HSYNC_CFGH_REG,&val); val = screen->mode.left_margin & 0xff; - anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val); + anx6345_i2c_write_p1_reg(client,HB_PORCHL_REG,&val); val = screen->mode.left_margin >> 8; - anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHH_REG,&val); + anx6345_i2c_write_p1_reg(client,HB_PORCHH_REG,&val); val = 0x13; - anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val); + anx6345_i2c_write_p1_reg(client,VID_CTRL10_REG,&val); //enable BIST. In normal mode, don't need to config this reg val = 0x08; - anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val); + anx6345_i2c_write_p1_reg(client, VID_CTRL4_REG, &val); printk("anx6345 enter bist mode\n"); return 0; } -#else -static int anx6345_bist_mode(struct i2c_client *client) + + +int anx6345_start_aux_transaction(struct i2c_client *client) { - char val = 0x00; - //these register are for bist mode - val = 0x2c; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val); - val = 0x06; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val); - val = 0x06; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val); - val = 0x02; - anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val); - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val); - val = 0x26; - anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val); - val = 0x50; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val); - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val); - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val); - val = 0x18; - anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val); - val = 0x10; - anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val); - val = 0x28; - anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val); - val = 0x13; - anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val); - //enable BIST. In normal mode, don't need to config this reg - val = 0x08; - anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val); - printk("anx6345 enter bist mode\n"); + char val; + int retval = 0; + int timeout_loop = 0; + int aux_timeout = 0; + - return 0; + anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val); + val |= AUX_EN; + anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val); + + anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val); + while (val & AUX_EN) { + aux_timeout++; + if ((DP_TIMEOUT_LOOP_CNT * 10) < aux_timeout) { + dev_err(&client->dev, "AUX CH enable timeout!\n"); + return -ETIMEDOUT; + } + anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val); + udelay(100); + } + + /* Is AUX CH command redply received? */ + anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val); + while (!(val & RPLY_RECEIV)) { + timeout_loop++; + if (DP_TIMEOUT_LOOP_CNT < timeout_loop) { + dev_err(&client->dev, "AUX CH command redply failed!\n"); + return -ETIMEDOUT; + } + anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val); + udelay(10); + } + + /* Clear interrupt source for AUX CH command redply */ + anx6345_i2c_write_p1_reg(client, DP_INT_STA, &val); + + /* Check AUX CH error access status */ + anx6345_i2c_read_p0_reg(client, AUX_CH_STA, &val); + if ((val & AUX_STATUS_MASK) != 0) { + dev_err(&client->dev, "AUX CH error happens: %d\n\n", + val & AUX_STATUS_MASK); + return -EREMOTEIO; + } + + return retval; } -#endif +int anx6345_dpcd_write_bytes(struct i2c_client *client, + unsigned int val_addr, + unsigned int count, + unsigned char data[]) +{ + char val; + unsigned int start_offset; + unsigned int cur_data_count; + unsigned int cur_data_idx; + int retval = 0; + + start_offset = 0; + while (start_offset < count) { + /* Buffer size of AUX CH is 16 * 4bytes */ + if ((count - start_offset) > 16) + cur_data_count = 16; + else + cur_data_count = count - start_offset; + + val = BUF_CLR; + anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val); + + val = AUX_ADDR_7_0(val_addr + start_offset); + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val); + val = AUX_ADDR_15_8(val_addr + start_offset); + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val); + val = AUX_ADDR_19_16(val_addr + start_offset); + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val); + + for (cur_data_idx = 0; cur_data_idx < cur_data_count; + cur_data_idx++) { + val = data[start_offset + cur_data_idx]; + anx6345_i2c_write_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val); + } + + /* + * Set DisplayPort transaction and write + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + val = AUX_LENGTH(cur_data_count) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val); + + /* Start AUX transaction */ + retval = anx6345_start_aux_transaction(client); + if (retval == 0) + break; + else + dev_dbg(&client->dev, "Aux Transaction fail!\n"); + + + start_offset += cur_data_count; + } + + return retval; +} + + +int anx6345_dpcd_read_bytes(struct i2c_client *client, + unsigned int val_addr, + unsigned int count, + unsigned char data[]) +{ + char val; + unsigned int start_offset; + unsigned int cur_data_count; + unsigned int cur_data_idx; + int i; + int retval = 0; + + start_offset = 0; + while (start_offset < count) { + /* Buffer size of AUX CH is 16 * 4bytes */ + if ((count - start_offset) > 16) + cur_data_count = 16; + else + cur_data_count = count - start_offset; + + /* AUX CH Request Transaction process */ + for (i = 0; i < 10; i++) { + /* Select DPCD device address */ + val = AUX_ADDR_7_0(val_addr + start_offset); + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val); + val = AUX_ADDR_15_8(val_addr + start_offset); + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val); + val = AUX_ADDR_19_16(val_addr + start_offset); + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val); + + /* + * Set DisplayPort transaction and read + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + val = AUX_LENGTH(cur_data_count) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val); + + val = BUF_CLR; + anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val); + + /* Start AUX transaction */ + retval = anx6345_start_aux_transaction(client); + if (retval == 0) + break; + else + dev_dbg(&client->dev, "Aux Transaction fail!\n"); + } + + for (cur_data_idx = 0; cur_data_idx < cur_data_count; + cur_data_idx++) { + anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val); + data[start_offset + cur_data_idx] = val; + dev_dbg(&client->dev, "0x%05x :0x%02x\n",cur_data_idx, val); + } + + start_offset += cur_data_count; + } + + return retval; +} + + +int anx6345_select_i2c_device(struct i2c_client *client, + unsigned int device_addr, + char val_addr) +{ + char val; + int retval; + + /* Set normal AUX CH command */ + anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val); + val &= ~ADDR_ONLY; + anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val); + /* Set EDID device address */ + val = device_addr; + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val); + val = 0; + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val); + anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val); + + /* Set offset from base address of EDID device */ + anx6345_i2c_write_p0_reg(client, BUF_DATA_0, &val_addr); + + /* + * Set I2C transaction and write address + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | + AUX_TX_COMM_WRITE; + anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val); + + /* Start AUX transaction */ + retval = anx6345_start_aux_transaction(client); + if (retval != 0) + dev_dbg(&client->dev, "Aux Transaction fail!\n"); + + return retval; +} + +int anx6345_edid_read_bytes(struct i2c_client *client, + unsigned int device_addr, + unsigned int val_addr, + unsigned char count, + unsigned char edid[]) +{ + char val; + unsigned int i; + unsigned int start_offset; + unsigned int cur_data_idx; + unsigned int cur_data_cnt; + unsigned int defer = 0; + int retval = 0; + + for (i = 0; i < count; i += 16) { + start_offset = i; + if ((count - start_offset) > 16) + cur_data_cnt = 16; + else + cur_data_cnt = count - start_offset; + /* + * If Rx sends defer, Tx sends only reads + * request without sending addres + */ + if (!defer) + retval = anx6345_select_i2c_device(client, + device_addr, val_addr + i); + else + defer = 0; + + /* + * Set I2C transaction and write data + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + val = AUX_LENGTH(cur_data_cnt) | AUX_TX_COMM_I2C_TRANSACTION | + AUX_TX_COMM_READ; + anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val); + + /* Start AUX transaction */ + retval = anx6345_start_aux_transaction(client); + if (retval < 0) + dev_dbg(&client->dev, "Aux Transaction fail!\n"); + + /* Check if Rx sends defer */ + anx6345_i2c_read_p0_reg(client, DP_AUX_RX_COMM, &val); + if (val == AUX_RX_COMM_AUX_DEFER || + val == AUX_RX_COMM_I2C_DEFER) { + dev_err(&client->dev, "Defer: %d\n\n", val); + defer = 1; + } + + + for (cur_data_idx = 0; cur_data_idx < cur_data_cnt; cur_data_idx++) { + anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val); + edid[i + cur_data_idx] = val; + dev_dbg(&client->dev, "0x%02x : 0x%02x\n", i + cur_data_idx, val); + } + } + + return retval; +} + +static int anx6345_read_edid(struct i2c_client *client) +{ + unsigned char edid[EDID_LENGTH * 2]; + unsigned char extend_block = 0; + unsigned char sum; + unsigned char test_vector; + int retval; + char addr; + struct edp_anx6345 *anx6345 = i2c_get_clientdata(client); + + + /* Read Extension Flag, Number of 128-byte EDID extension blocks */ + retval = anx6345_edid_read_bytes(client, EDID_ADDR, + EDID_EXTENSION_FLAG,1,&extend_block); + if (retval < 0) { + dev_err(&client->dev, "EDID extension flag failed!\n"); + return -EIO; + } + + if (extend_block > 0) { + dev_dbg(&client->dev, "EDID data includes a single extension!\n"); + + /* Read EDID data */ + retval = anx6345_edid_read_bytes(client, EDID_ADDR, + EDID_HEADER, + EDID_LENGTH, + &edid[EDID_HEADER]); + if (retval != 0) { + dev_err(&client->dev, "EDID Read failed!\n"); + return -EIO; + } + sum = edp_calc_edid_check_sum(edid); + if (sum != 0) { + dev_warn(&client->dev, "EDID bad checksum!\n"); + return 0; + } + + /* Read additional EDID data */ + retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_LENGTH, + EDID_LENGTH, &edid[EDID_LENGTH]); + if (retval != 0) { + dev_err(&client->dev, "EDID Read failed!\n"); + return -EIO; + } + sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]); + if (sum != 0) { + dev_warn(&client->dev, "EDID bad checksum!\n"); + return 0; + } + + retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST, + 1, &test_vector); + if (retval < 0) { + dev_err(&client->dev, "DPCD EDID Read failed!\n"); + return retval; + } + + if (test_vector & DPCD_TEST_EDID_READ) { + retval = anx6345_dpcd_write_bytes(client, + DPCD_TEST_EDID_CHECKSUM,1, + &edid[EDID_LENGTH + EDID_CHECKSUM]); + if (retval < 0) { + dev_err(&client->dev, "DPCD EDID Write failed!\n"); + return retval; + } + + addr = DPCD_TEST_EDID_CHECKSUM_WRITE; + retval = anx6345_dpcd_write_bytes(client, + DPCD_TEST_RESPONSE, 1, &addr); + if (retval < 0) { + dev_err(&client->dev, "DPCD EDID checksum failed!\n"); + return retval; + } + } + } else { + dev_info(&client->dev, "EDID data does not include any extensions.\n"); + + /* Read EDID data */ + retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_HEADER, + EDID_LENGTH, &edid[EDID_HEADER]); + if (retval != 0) { + dev_err(&client->dev, "EDID Read failed!\n"); + return -EIO; + } + + sum = edp_calc_edid_check_sum(edid); + if (sum != 0) { + dev_warn(&client->dev, "EDID bad checksum!\n"); + return 0; + } + + retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST, + 1,&test_vector); + if (retval < 0) { + dev_err(&client->dev, "DPCD EDID Read failed!\n"); + return retval; + } + + if (test_vector & DPCD_TEST_EDID_READ) { + retval = anx6345_dpcd_write_bytes(client, + DPCD_TEST_EDID_CHECKSUM, 1, + &edid[EDID_CHECKSUM]); + if (retval < 0) { + dev_err(&client->dev, "DPCD EDID Write failed!\n"); + return retval; + } + addr = DPCD_TEST_EDID_CHECKSUM_WRITE; + retval = anx6345_dpcd_write_bytes(client, DPCD_TEST_RESPONSE, + 1, &addr); + if (retval < 0) { + dev_err(&client->dev, "DPCD EDID checksum failed!\n"); + return retval; + } + } + } + fb_edid_to_monspecs(edid, &anx6345->specs); + dev_info(&client->dev, "EDID Read success!\n"); + return 0; +} static int anx6345_init(struct i2c_client *client) { @@ -744,7 +1084,8 @@ static int anx6345_init(struct i2c_client *client) char i = 0; char lc,bw; char cnt = 50; - + u8 buf[12]; + val = 0x30; anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val); @@ -752,10 +1093,10 @@ static int anx6345_init(struct i2c_client *client) for(i=0;i<50;i++) { - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); - anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); - if((val&SP_TX_SYS_CTRL1_DET_STA)!=0) + anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val); + anx6345_i2c_write_p0_reg(client, SYS_CTRL1_REG, &val); + anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val); + if((val&SYS_CTRL1_DET_STA)!=0) { break; } @@ -768,10 +1109,10 @@ static int anx6345_init(struct i2c_client *client) //check whether clock is stable for(i=0;i<50;i++) { - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val); - if((val&SP_TX_SYS_CTRL2_CHA_STA)==0) + anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val); + anx6345_i2c_write_p0_reg(client,SYS_CTRL2_REG, &val); + anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val); + if((val&SYS_CTRL2_CHA_STA)==0) { break; } @@ -779,49 +1120,52 @@ static int anx6345_init(struct i2c_client *client) } if(i>49) printk("clk is not stable\n"); + + anx6345_dpcd_read_bytes(client, DPCD_REV, 12, buf); + anx6345_read_edid(client); //VESA range, 6bits BPC, RGB val = 0x00; - anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val); + anx6345_i2c_write_p1_reg(client, VID_CTRL2_REG, &val); //ANX6345 chip pll setting val = 0x00; - anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00 + anx6345_i2c_write_p0_reg(client, PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00 //ANX chip analog setting val = 0x70; anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); //UPDATE: FROM 0XF0 TO 0X70 val = 0x30; - anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val); + anx6345_i2c_write_p0_reg(client, LINK_DEBUG_REG, &val); //force HPD - //anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val); + //anx6345_i2c_write_p0_reg(client, SYS_CTRL3_REG, &val); //reset AUX - anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); - val |= SP_TX_AUX_RST; - anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); - val &= ~SP_TX_AUX_RST; - anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); + anx6345_i2c_read_p1_reg(client, RST_CTRL2_REG, &val); + val |= AUX_RST; + anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val); + val &= ~AUX_RST; + anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val); //Select 2.7G val = 0x0a; - anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val); + anx6345_i2c_write_p0_reg(client, LINK_BW_SET_REG, &val); //Select 2 lanes val = 0x02; - anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val); + anx6345_i2c_write_p0_reg(client,LANE_COUNT_SET_REG,&val); - val = SP_TX_LINK_TRAINING_CTRL_EN; - anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val); + val = LINK_TRAINING_CTRL_EN; + anx6345_i2c_write_p0_reg(client, LINK_TRAINING_CTRL_REG, &val); mdelay(5); - anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val); + anx6345_i2c_read_p0_reg(client, LINK_TRAINING_CTRL_REG, &val); while((val&0x80)&&(cnt)) //UPDATE: FROM 0X01 TO 0X80 { printk("Waiting...\n"); mdelay(5); - anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val); + anx6345_i2c_read_p0_reg(client,LINK_TRAINING_CTRL_REG,&val); cnt--; } if(cnt <= 0) @@ -842,15 +1186,15 @@ static int anx6345_init(struct i2c_client *client) #else val = 0x81; #endif - anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val); + anx6345_i2c_write_p1_reg(client,VID_CTRL1_REG,&val); anx_video_map_config(client); //force HPD and stream valid val = 0x33; - anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val); + anx6345_i2c_write_p0_reg(client,SYS_CTRL3_REG,&val); - anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc); - anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw); + anx6345_i2c_read_p0_reg(client,LANE_COUNT_SET_REG, &lc); + anx6345_i2c_read_p0_reg(client,LINK_BW_SET_REG, &bw); printk("%s..lc:%d--bw:%d\n",__func__,lc,bw); return 0; diff --git a/drivers/video/rockchip/transmitter/dpcd_edid.h b/drivers/video/rockchip/transmitter/dpcd_edid.h new file mode 100644 index 000000000000..405283e41aff --- /dev/null +++ b/drivers/video/rockchip/transmitter/dpcd_edid.h @@ -0,0 +1,134 @@ +#ifndef __DPCD_EDID_H +#define __DPCD_EDID_H +#include "../../edid.h" + +#define DPCD_REV 0x00 +#define DPCD_MAX_LINK_RATE 0x01 +#define DPCD_MAX_LANE_CNT 0x02 + +#define DPCD_MAX_DOWNSPREAD 0x03 +#define DPCD_NORP 0x04 +#define DPCD_DOWNSTREAMPORT_PRESENT 0x05 + +#define DPCD_RECEIVE_PORT0_CAP_0 0x08 +#define DPCD_RECEIVE_PORT0_CAP_1 0x09 +#define DPCD_RECEIVE_PORT0_CAP_2 0x0a +#define DPCD_RECEIVE_PORT0_CAP_3 0x0b + +#define DPCD_LINK_BW_SET 0x100 +#define DPCD_LANE_CNT_SET 0x101 +#define DPCD_TRAINING_PATTERN_SET 0x102 +#define DPCD_TRAINING_LANE0_SET 0x103 +#define DPCD_TRAINING_LANE1_SET 0x104 +#define DPCD_TRAINING_LANE2_SET 0x105 +#define DPCD_TRAINING_LANE3_SET 0x106 +#define DPCD_DOWNSPREAD_CTRL 0x107 + +#define DPCD_SINK_COUNT 0x200 +#define DPCD_DEVICE_SERVICE_IRQ_VECTOR 0x201 +#define DPCD_LANE0_1_STATUS 0x202 +#define DPCD_LANE2_3_STATUS 0x203 +#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204 +#define DPCD_SINK_STATUS 0x205 +#define DPCD_ADJUST_REQUEST_LANE0_1 0x206 +#define DPCD_ADJUST_REQUEST_LANE2_3 0x207 +#define DPCD_TRAINING_SCORE_LANE0 0x208 +#define DPCD_TRAINING_SCORE_LANE1 0x209 +#define DPCD_TRAINING_SCORE_LANE2 0x20a +#define DPCD_TRAINING_SCORE_LANE3 0x20b +#define DPCD_SINK_POWER_STATE 0x0600 + +/* DPCD_ADDR_MAX_LANE_COUNT */ +#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) +#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) + +/* DPCD_ADDR_LANE_COUNT_SET */ +#define DPCD_ENHANCED_FRAME_EN (0x1 << 7) +#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) + +/* DPCD_ADDR_TRAINING_PATTERN_SET */ +#define DPCD_SCRAMBLING_DISABLED (0x1 << 5) +#define DPCD_SCRAMBLING_ENABLED (0x0 << 5) +#define DPCD_TRAINING_PATTERN_2 (0x2 << 0) +#define DPCD_TRAINING_PATTERN_1 (0x1 << 0) +#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0) + +/* DPCD_ADDR_TRAINING_LANE0_SET */ +#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5) +#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) +#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) +#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3) +#define DPCD_MAX_SWING_REACHED (0x1 << 2) +#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) +#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) +#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0) + +/* DPCD_ADDR_LANE0_1_STATUS */ +#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2) +#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1) +#define DPCD_LANE_CR_DONE (0x1 << 0) +#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \ + DPCD_LANE_CHANNEL_EQ_DONE|\ + DPCD_LANE_SYMBOL_LOCKED) + +#define DPCD_TEST_REQUEST 0x218 +#define DPCD_TEST_LINK_RATE 0x219 + +#define DPCD_TEST_LANE_COUNT 0x220 +#define DPCD_TEST_RESPONSE 0x260 +#define DPCD_TEST_EDID_CHECKSUM 0x261 +#define TEST_ACK 0x01 +#define DPCD_TEST_EDID_Checksum_Write 0x04//bit position + +#define DPCD_TEST_EDID_Checksum 0x261 + + +#define DPCD_SPECIFIC_INTERRUPT 0x10 +#define DPCD_USER_COMM1 0x22//define for downstream HDMI Rx sense detection + +#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) +#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) +#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) + +#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) +#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) + +/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */ +#define DPCD_LINK_STATUS_UPDATED (0x1 << 7) +#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6) +#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0) + +/* DPCD_ADDR_TEST_REQUEST */ +#define DPCD_TEST_EDID_READ (0x1 << 2) + +/* DPCD_ADDR_TEST_RESPONSE */ +#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2) + +/* DPCD_ADDR_SINK_POWER_STATE */ +#define DPCD_SET_POWER_STATE_D0 (0x1 << 0) +#define DPCD_SET_POWER_STATE_D4 (0x2 << 0) + + +/* + * EDID device address is 0x50. + * However, if necessary, you must have set upper address + * into E-EDID in I2C device, 0x30. + */ + +#define EDID_ADDR 0x50 +#define E_EDID_ADDR 0x30 +#define EDID_EXTENSION_FLAG 0x7e +#define EDID_CHECKSUM 0x7f + +static unsigned char edp_calc_edid_check_sum(unsigned char *edid_data) +{ + int i; + unsigned char sum = 0; + + for (i = 0; i < EDID_LENGTH; i++) + sum = sum + edid_data[i]; + + return sum; +} + +#endif -- 2.34.1