From bf3ef90c3468895100143380f4a68afccdf755c7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Tue, 7 Aug 2012 19:36:13 +0800 Subject: [PATCH] rk2928: fix rk2928_cpu_axi_init --- arch/arm/mach-rk2928/common.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rk2928/common.c b/arch/arm/mach-rk2928/common.c index 36b625dac57f..5585deb22ce0 100644 --- a/arch/arm/mach-rk2928/common.c +++ b/arch/arm/mach-rk2928/common.c @@ -18,21 +18,15 @@ static void __init rk2928_cpu_axi_init(void) { -#if 0 writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0088); // cpu0 - writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0108); // dmac1 writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0188); // cpu1r writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0388); // cpu1w writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x4008); // peri writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x5008); // gpu writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x6008); // vpu - writel_relaxed(0xa, RK2928_CPU_AXI_BUS_BASE + 0x7008); // lcdc0 - writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7088); // cif0 - writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7108); // ipp - writel_relaxed(0xa, RK2928_CPU_AXI_BUS_BASE + 0x7188); // lcdc1 - writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7208); // cif1 + writel_relaxed(0xa, RK2928_CPU_AXI_BUS_BASE + 0x7188); // lcdc + writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7208); // cif writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7288); // rga -#endif writel_relaxed(0x3f, RK2928_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency dsb(); } -- 2.34.1