From c0acf5da01c8df45f569ca0400eae4a4bd0d0c15 Mon Sep 17 00:00:00 2001 From: dkl Date: Sun, 30 Mar 2014 16:37:47 +0800 Subject: [PATCH] clk: rockchip: add rkclk_init_enable and open rk3288 gating --- arch/arm/boot/dts/rk3288-clocks.dtsi | 24 ++++---- arch/arm/boot/dts/rk3288.dtsi | 91 ++++++++++++++++++++++++++++ drivers/clk/clk-gate.c | 4 +- drivers/clk/rockchip/clk.c | 49 ++++++++++++++- 4 files changed, 152 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi index 76c8214d52f9..a2b48dee651a 100755 --- a/arch/arm/boot/dts/rk3288-clocks.dtsi +++ b/arch/arm/boot/dts/rk3288-clocks.dtsi @@ -2012,14 +2012,14 @@ <&dummy>, <&dummy>; clock-output-names = - "reserved", "core_apll", + "reserved", "reserved", /* do not use bit1 = "core_apll" */ "clk_arm_gpll", "g_aclk_bus", "hclk_bus", "pclk_bus", "reserved", "aclk_bus_2pmu", "reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/ - "clk_bus_gpll", "clk_bus_cpll", + "reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/ "clk_acc_efuse", "reserved", "reserved", "reserved"; @@ -2078,7 +2078,7 @@ <&dummy>, <&dummy>; clock-output-names = - "aclk_peri", "g_aclk_periph", + "aclk_peri", "reserved", /*"g_aclk_periph",*/ "hclk_peri", "pclk_peri", "reserved", "clk_mac_pll", @@ -2354,7 +2354,7 @@ "g_hclk_spdif", "g_h_spdif_8ch", "g_aclk_dmac1", "g_aclk_strc_sys", - "g_p_ddrupctl0", "g_pclk_publ0"; + "reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/ rockchip,suspend-clkgating-setting=<0xe2f0 0xe2f0>; #clock-cells = <1>; @@ -2377,11 +2377,11 @@ <&dummy>, <&dummy>; clock-output-names = - "g_p_ddrupctl1", "g_pclk_publ1", - "g_p_efuse_1024", "g_pclk_tzpc", + "reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/ + "g_p_efuse_1024", "g_pclk_tzpc", "reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/ - "g_aclk_crypto", "g_hclk_crypto", + "g_aclk_crypto", "g_hclk_crypto", "g_aclk_ccp", "g_pclk_uart2", "g_p_efuse_256", "g_pclk_rkpwm", @@ -2416,8 +2416,8 @@ "clk_l2ram", "aclk_core_m0", "aclk_core_mp", "atclk_core", - "pclk_dbg_src", "g_dbg_core_clk", - "g_cs_dbg_clk", "g_pclk_core_niu", + "pclk_dbg_src", "reserved", /*"g_dbg_core_clk",*/ + "reserved", "reserved", /*"g_cs_dbg_clk", "g_pclk_core_niu",*/ "reserved", "reserved", "reserved", "reserved"; @@ -2509,7 +2509,7 @@ <&aclk_vio0>, <&hclk_vio>; clock-output-names = - "g_aclk_rga", "g_hclk_rga", + "reserved", /*"g_aclk_rga",*/ "g_hclk_rga", "g_aclk_iep", "g_hclk_iep", "g_aclk_lcdc_iep", "g_aclk_lcdc0", @@ -2518,7 +2518,7 @@ "g_hclk_lcdc1", "g_h_vio_ahb", "g_hclk_vio_niu", "g_aclk_vio0_niu", - "g_aclk_vio1_niu", "g_aclk_vio2_niu", + "g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu",*/ "g_aclk_vip", "g_hclk_vip"; rockchip,suspend-clkgating-setting=<0x0 0x0>; @@ -2608,7 +2608,7 @@ <&dummy>, <&dummy>; clock-output-names = - "g_aclk_gpu", "reserved", + "reserved", /*"g_aclk_gpu",*/ "reserved", "reserved", "reserved", "reserved", "reserved", diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 7ecf677d1490..84b28b148fb9 100755 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -471,6 +471,97 @@ <&clk_tspout 80000000>, <&clk_mac 125000000>; }; + clocks-enable { + compatible = "rockchip,clocks-enable"; + clocks = + /*PD_CORE*/ + <&clk_gates0 2>, <&clk_core0>, + <&clk_core1>, <&clk_core2>, + <&clk_core3>, <&clk_l2ram>, + <&aclk_core_m0>, <&aclk_core_mp>, + <&atclk_core>, <&pclk_dbg_src>, + + /*PD_BUS*/ + <&aclk_bus>, <&clk_gates0 3>, + <&hclk_bus>, <&pclk_bus>, + <&clk_gates13 8>, <&clk_crypto>, + <&clk_gates0 7>, + + /*TIMER*/ + <&clk_gates1 0>, <&clk_gates1 1>, + <&clk_gates1 2>, <&clk_gates1 3>, + <&clk_gates1 4>, <&clk_gates1 5>, + + <&pclk_pd_alive>, <&pclk_pd_pmu>, + + /*PD_PERI*/ + <&aclk_peri>, <&hclk_peri>, + <&pclk_peri>, + + /*JTAG*/ + /*<&clk_gates4 14>,*/ + + /*aclk_bus*/ + <&clk_gates10 5>,/*aclk_intmem0*/ + <&clk_gates10 6>,/*aclk_intmem1*/ + <&clk_gates10 7>,/*aclk_intmem2*/ + <&clk_gates10 12>,/*aclk_dma1*/ + <&clk_gates10 13>,/*aclk_strc_sys*/ + <&clk_gates10 4>,/*aclk_intmem*/ + <&clk_gates11 6>,/*aclk_crypto*/ + <&clk_gates11 8>,/*aclk_ccp*/ + + /*hclk_bus*/ + <&clk_gates11 7>,/*hclk_crypto*/ + <&clk_gates10 9>,/*hclk_rom*/ + + /*pclk_bus*/ + <&clk_gates10 1>,/*pclk_timer*/ + + /*aclk_peri*/ + <&clk_gates6 2>,/*aclk_peri_axi_matrix*/ + <&clk_gates6 3>,/*aclk_dmac2*/ + <&clk_gates7 11>,/*aclk_peri_niu*/ + <&clk_gates8 12>,/*aclk_peri_mmu*/ + + /*hclk_peri*/ + <&clk_gates6 0>,/*hclk_peri_matrix*/ + <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/ + <&clk_gates7 12>,/*hclk_emem_peri*/ + <&clk_gates7 13>,/*hclk_mem_peri*/ + + /*pclk_peri*/ + <&clk_gates6 1>,/*pclk_peri_axi_matrix*/ + + /*pclk_pd_alive*/ + <&clk_gates14 11>,/*pclk_grf*/ + <&clk_gates14 12>,/*pclk_alive_niu*/ + + /*pclk_pd_pmu*/ + <&clk_gates17 0>,/*pclk_pmu*/ + <&clk_gates17 1>,/*pclk_intmem1*/ + <&clk_gates17 2>,/*pclk_pmu_niu*/ + <&clk_gates17 3>,/*pclk_sgrf*/ + + /*hclk_vio*/ + <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/ + <&clk_gates15 10>,/*hclk_vio_niu*/ + <&clk_gates16 10>,/*hclk_vio2_h2p*/ + <&clk_gates16 11>,/*pclk_vio2_h2p*/ + + /*aclk_vio0*/ + <&clk_gates15 11>,/*aclk_vio0_niu*/ + + /*aclk_vio1*/ + <&clk_gates15 12>,/*aclk_vio1_niu*/ + + /*HDMI*/ + <&clk_gates5 12>,/*hdmi_hdcp_clk*/ + + /*UART*/ + <&clk_gates11 9>;/*pclk_uart2*/ + }; + i2c0: i2c@ff650000 { compatible = "rockchip,rk30-i2c"; reg = <0xff650000 0x1000>; diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 33adb0f5ddd4..790306e921c8 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -74,14 +74,14 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) static int clk_gate_enable(struct clk_hw *hw) { - //clk_gate_endisable(hw, 1); + clk_gate_endisable(hw, 1); return 0; } static void clk_gate_disable(struct clk_hw *hw) { - //clk_gate_endisable(hw, 0); + clk_gate_endisable(hw, 0); } static int clk_gate_is_enabled(struct clk_hw *hw) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 8816392e444a..c05687927cfd 100755 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -1658,7 +1658,7 @@ void rk_clk_test(void) {} #endif EXPORT_SYMBOL_GPL(rk_clk_test); -void rkclk_init_clks(struct device_node *node); +void __init rkclk_init_clks(struct device_node *node); static struct device_node * clk_root_node=NULL; static void __init rk_clk_tree_init(struct device_node *np) @@ -1796,7 +1796,50 @@ const char *of_clk_init_parent_get_info(struct device_node *np, int index, return clk_name; } -void rkclk_init_clks(struct device_node *np) +static int __init rkclk_init_enable(void) +{ + struct device_node *node; + int cnt, i, ret = 0; + const char *clk_name; + struct clk *clk; + + + node = of_find_node_by_name(NULL, "clocks-enable"); + if (!node) { + clk_err("%s: can not get clocks-enable node\n", __func__); + return -EINVAL; + } + + cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells"); + if (cnt < 0) { + return -EINVAL; + } else { + clk_debug("%s: cnt = %d\n", __func__, cnt); + } + + for (i = 0; i < cnt ; i++) { + clk_name = of_clk_get_parent_name(node, i); + clk = clk_get(NULL, clk_name); + if (IS_ERR_OR_NULL(clk)) { + clk_err("%s: fail to get %s\n", __func__, clk_name); + return -EINVAL; + } + + ret = clk_prepare_enable(clk); + if (ret) { + clk_err("%s: fail to prepare_enable %s\n", __func__, + clk_name); + return ret; + } else { + clk_debug("%s: prepare_enable %s OK\n", __func__, + clk_name); + } + } + + return ret; +} + +void __init rkclk_init_clks(struct device_node *np) { //struct device_node *np; int i,cnt_parent,cnt_rate; @@ -1855,6 +1898,8 @@ void rkclk_init_clks(struct device_node *np) clk_rate); } + rkclk_init_enable(); + } u32 clk_suspend_clkgt_info_get(u32 *clk_ungt_msk,u32 *clk_ungt_msk_last,u32 buf_cnt) -- 2.34.1