From c196bfecd6cd6c601a67e1d04a4a16f6833f5acf Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Wed, 10 Jun 2015 16:52:32 +0000 Subject: [PATCH] [Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239477 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Disassembler/HexagonDisassembler.cpp | 118 ++++ lib/Target/Hexagon/HexagonOperands.td | 47 +- .../MCTargetDesc/HexagonAsmBackend.cpp | 25 +- .../MCTargetDesc/HexagonELFObjectWriter.cpp | 502 +++++++----------- test/CodeGen/Hexagon/signed_immediates.ll | 99 ++++ test/MC/Disassembler/Hexagon/alu32_alu.txt | 2 +- 6 files changed, 461 insertions(+), 332 deletions(-) create mode 100644 test/CodeGen/Hexagon/signed_immediates.ll diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 14f9d777580..9cc1e944d35 100644 --- a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -69,6 +69,33 @@ static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, raw_ostream &os); static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst); +static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, + const void *Decoder); + static const uint16_t IntRegDecoderTable[] = { Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, @@ -356,6 +383,97 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return Result; } +static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<16>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<12>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<11>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<12>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<13>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<14>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<10>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, + const void *Decoder) { + uint64_t imm = SignExtend64<8>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<6>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<4>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<5>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<6>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + uint64_t imm = SignExtend64<7>(tmp); + MI.addOperand(MCOperand::createImm(imm)); + return MCDisassembler::Success; +} + // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td enum subInstBinaryValues { V4_SA1_addi_BITS = 0x0000, diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td index be8204b7de5..d5191dc6ab2 100644 --- a/lib/Target/Hexagon/HexagonOperands.td +++ b/lib/Target/Hexagon/HexagonOperands.td @@ -7,32 +7,24 @@ // //===----------------------------------------------------------------------===// +def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; } +def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; } +def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; } +def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; } + // Immediate operands. let PrintMethod = "printImmOperand" in { - // f32Ext type is used to identify constant extended floating point immediates. - def f32Ext : Operand; def s32Imm : Operand; - def s26_6Imm : Operand; - def s16Imm : Operand; - def s12Imm : Operand; - def s11Imm : Operand; - def s11_0Imm : Operand; - def s11_1Imm : Operand; - def s11_2Imm : Operand; - def s11_3Imm : Operand; - def s10Imm : Operand; - def s9Imm : Operand; - def m9Imm : Operand; def s8Imm : Operand; def s8Imm64 : Operand; def s6Imm : Operand; def s6_3Imm : Operand; def s4Imm : Operand; - def s4_0Imm : Operand; - def s4_1Imm : Operand; - def s4_2Imm : Operand; - def s4_3Imm : Operand; + def s4_0Imm : Operand { let DecoderMethod = "s4_0ImmDecoder"; } + def s4_1Imm : Operand { let DecoderMethod = "s4_1ImmDecoder"; } + def s4_2Imm : Operand { let DecoderMethod = "s4_2ImmDecoder"; } + def s4_3Imm : Operand { let DecoderMethod = "s4_3ImmDecoder"; } def u64Imm : Operand; def u32Imm : Operand; def u26_6Imm : Operand; @@ -446,17 +438,18 @@ def SetClr3ImmPred : PatLeaf<(i32 imm), [{ // Extendable immediate operands. let PrintMethod = "printExtOperand" in { - def s16Ext : Operand; - def s12Ext : Operand; - def s10Ext : Operand; - def s9Ext : Operand; - def s8Ext : Operand; + def f32Ext : Operand; + def s16Ext : Operand { let DecoderMethod = "s16ImmDecoder"; } + def s12Ext : Operand { let DecoderMethod = "s12ImmDecoder"; } + def s11_0Ext : Operand { let DecoderMethod = "s11_0ImmDecoder"; } + def s11_1Ext : Operand { let DecoderMethod = "s11_1ImmDecoder"; } + def s11_2Ext : Operand { let DecoderMethod = "s11_2ImmDecoder"; } + def s11_3Ext : Operand { let DecoderMethod = "s11_3ImmDecoder"; } + def s10Ext : Operand { let DecoderMethod = "s10ImmDecoder"; } + def s9Ext : Operand { let DecoderMethod = "s90ImmDecoder"; } + def s8Ext : Operand { let DecoderMethod = "s8ImmDecoder"; } def s7Ext : Operand; - def s6Ext : Operand; - def s11_0Ext : Operand; - def s11_1Ext : Operand; - def s11_2Ext : Operand; - def s11_3Ext : Operand; + def s6Ext : Operand { let DecoderMethod = "s6_0ImmDecoder"; } def u6Ext : Operand; def u7Ext : Operand; def u8Ext : Operand; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 920988c1e83..99ea2fabf86 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -17,11 +17,14 @@ #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; using namespace Hexagon; +#define DEBUG_TYPE "hexagon-asm-backend" + namespace { class HexagonAsmBackend : public MCAsmBackend { @@ -278,8 +281,26 @@ public: llvm_unreachable("relaxInstruction() unimplemented"); } - bool writeNopData(uint64_t /*Count*/, - MCObjectWriter * /*OW*/) const override { + bool writeNopData(uint64_t Count, + MCObjectWriter * OW) const override { + static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP. + ParseIn = 0x00004000, // In packet parse-bits. + ParseEnd = 0x0000c000; // End of packet parse-bits. + + while(Count % HEXAGON_INSTR_SIZE) { + DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << + Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); + --Count; + OW->write8(0); + } + + while(Count) { + Count -= HEXAGON_INSTR_SIZE; + // Close the packet whenever a multiple of the maximum packet size remains + uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))? + ParseIn: ParseEnd; + OW->write32(Nopcode | ParseBits); + } return true; } }; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp index 843072302b2..da5d4d1da69 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp @@ -38,311 +38,209 @@ HexagonELFObjectWriter::HexagonELFObjectWriter(uint8_t OSABI, StringRef C) /*HasRelocationAddend*/ true), CPU(C) {} -unsigned HexagonELFObjectWriter::GetRelocType(MCValue const &/*Target*/, +unsigned HexagonELFObjectWriter::GetRelocType(MCValue const & /*Target*/, MCFixup const &Fixup, bool IsPCRel) const { - // determine the type of the relocation - unsigned Type = (unsigned)ELF::R_HEX_NONE; - unsigned Kind = (unsigned)Fixup.getKind(); - - switch (Kind) { - default: - DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n"); - llvm_unreachable("Unimplemented Fixup kind!"); - break; - case FK_Data_4: - Type = (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32; - break; - case FK_PCRel_4: - Type = ELF::R_HEX_32_PCREL; - break; - case FK_Data_2: - Type = ELF::R_HEX_16; - break; - case FK_Data_1: - Type = ELF::R_HEX_8; - break; - case fixup_Hexagon_B22_PCREL: - Type = ELF::R_HEX_B22_PCREL; - break; - case fixup_Hexagon_B15_PCREL: - Type = ELF::R_HEX_B15_PCREL; - break; - case fixup_Hexagon_B7_PCREL: - Type = ELF::R_HEX_B7_PCREL; - break; - case fixup_Hexagon_LO16: - Type = ELF::R_HEX_LO16; - break; - case fixup_Hexagon_HI16: - Type = ELF::R_HEX_HI16; - break; - case fixup_Hexagon_32: - Type = ELF::R_HEX_32; - break; - case fixup_Hexagon_16: - Type = ELF::R_HEX_16; - break; - case fixup_Hexagon_8: - Type = ELF::R_HEX_8; - break; - case fixup_Hexagon_GPREL16_0: - Type = ELF::R_HEX_GPREL16_0; - break; - case fixup_Hexagon_GPREL16_1: - Type = ELF::R_HEX_GPREL16_1; - break; - case fixup_Hexagon_GPREL16_2: - Type = ELF::R_HEX_GPREL16_2; - break; - case fixup_Hexagon_GPREL16_3: - Type = ELF::R_HEX_GPREL16_3; - break; - case fixup_Hexagon_HL16: - Type = ELF::R_HEX_HL16; - break; - case fixup_Hexagon_B13_PCREL: - Type = ELF::R_HEX_B13_PCREL; - break; - case fixup_Hexagon_B9_PCREL: - Type = ELF::R_HEX_B9_PCREL; - break; - case fixup_Hexagon_B32_PCREL_X: - Type = ELF::R_HEX_B32_PCREL_X; - break; - case fixup_Hexagon_32_6_X: - Type = ELF::R_HEX_32_6_X; - break; - case fixup_Hexagon_B22_PCREL_X: - Type = ELF::R_HEX_B22_PCREL_X; - break; - case fixup_Hexagon_B15_PCREL_X: - Type = ELF::R_HEX_B15_PCREL_X; - break; - case fixup_Hexagon_B13_PCREL_X: - Type = ELF::R_HEX_B13_PCREL_X; - break; - case fixup_Hexagon_B9_PCREL_X: - Type = ELF::R_HEX_B9_PCREL_X; - break; - case fixup_Hexagon_B7_PCREL_X: - Type = ELF::R_HEX_B7_PCREL_X; - break; - case fixup_Hexagon_16_X: - Type = ELF::R_HEX_16_X; - break; - case fixup_Hexagon_12_X: - Type = ELF::R_HEX_12_X; - break; - case fixup_Hexagon_11_X: - Type = ELF::R_HEX_11_X; - break; - case fixup_Hexagon_10_X: - Type = ELF::R_HEX_10_X; - break; - case fixup_Hexagon_9_X: - Type = ELF::R_HEX_9_X; - break; - case fixup_Hexagon_8_X: - Type = ELF::R_HEX_8_X; - break; - case fixup_Hexagon_7_X: - Type = ELF::R_HEX_7_X; - break; - case fixup_Hexagon_6_X: - Type = ELF::R_HEX_6_X; - break; - case fixup_Hexagon_32_PCREL: - Type = ELF::R_HEX_32_PCREL; - break; - case fixup_Hexagon_COPY: - Type = ELF::R_HEX_COPY; - break; - case fixup_Hexagon_GLOB_DAT: - Type = ELF::R_HEX_GLOB_DAT; - break; - case fixup_Hexagon_JMP_SLOT: - Type = ELF::R_HEX_JMP_SLOT; - break; - case fixup_Hexagon_RELATIVE: - Type = ELF::R_HEX_RELATIVE; - break; - case fixup_Hexagon_PLT_B22_PCREL: - Type = ELF::R_HEX_PLT_B22_PCREL; - break; - case fixup_Hexagon_GOTREL_LO16: - Type = ELF::R_HEX_GOTREL_LO16; - break; - case fixup_Hexagon_GOTREL_HI16: - Type = ELF::R_HEX_GOTREL_HI16; - break; - case fixup_Hexagon_GOTREL_32: - Type = ELF::R_HEX_GOTREL_32; - break; - case fixup_Hexagon_GOT_LO16: - Type = ELF::R_HEX_GOT_LO16; - break; - case fixup_Hexagon_GOT_HI16: - Type = ELF::R_HEX_GOT_HI16; - break; - case fixup_Hexagon_GOT_32: - Type = ELF::R_HEX_GOT_32; - break; - case fixup_Hexagon_GOT_16: - Type = ELF::R_HEX_GOT_16; - break; - case fixup_Hexagon_DTPMOD_32: - Type = ELF::R_HEX_DTPMOD_32; - break; - case fixup_Hexagon_DTPREL_LO16: - Type = ELF::R_HEX_DTPREL_LO16; - break; - case fixup_Hexagon_DTPREL_HI16: - Type = ELF::R_HEX_DTPREL_HI16; - break; - case fixup_Hexagon_DTPREL_32: - Type = ELF::R_HEX_DTPREL_32; - break; - case fixup_Hexagon_DTPREL_16: - Type = ELF::R_HEX_DTPREL_16; - break; - case fixup_Hexagon_GD_PLT_B22_PCREL: - Type = ELF::R_HEX_GD_PLT_B22_PCREL; - break; - case fixup_Hexagon_LD_PLT_B22_PCREL: - Type = ELF::R_HEX_LD_PLT_B22_PCREL; - break; - case fixup_Hexagon_GD_GOT_LO16: - Type = ELF::R_HEX_GD_GOT_LO16; - break; - case fixup_Hexagon_GD_GOT_HI16: - Type = ELF::R_HEX_GD_GOT_HI16; - break; - case fixup_Hexagon_GD_GOT_32: - Type = ELF::R_HEX_GD_GOT_32; - break; - case fixup_Hexagon_GD_GOT_16: - Type = ELF::R_HEX_GD_GOT_16; - break; - case fixup_Hexagon_LD_GOT_LO16: - Type = ELF::R_HEX_LD_GOT_LO16; - break; - case fixup_Hexagon_LD_GOT_HI16: - Type = ELF::R_HEX_LD_GOT_HI16; - break; - case fixup_Hexagon_LD_GOT_32: - Type = ELF::R_HEX_LD_GOT_32; - break; - case fixup_Hexagon_LD_GOT_16: - Type = ELF::R_HEX_LD_GOT_16; - break; - case fixup_Hexagon_IE_LO16: - Type = ELF::R_HEX_IE_LO16; - break; - case fixup_Hexagon_IE_HI16: - Type = ELF::R_HEX_IE_HI16; - break; - case fixup_Hexagon_IE_32: - Type = ELF::R_HEX_IE_32; - break; - case fixup_Hexagon_IE_GOT_LO16: - Type = ELF::R_HEX_IE_GOT_LO16; - break; - case fixup_Hexagon_IE_GOT_HI16: - Type = ELF::R_HEX_IE_GOT_HI16; - break; - case fixup_Hexagon_IE_GOT_32: - Type = ELF::R_HEX_IE_GOT_32; - break; - case fixup_Hexagon_IE_GOT_16: - Type = ELF::R_HEX_IE_GOT_16; - break; - case fixup_Hexagon_TPREL_LO16: - Type = ELF::R_HEX_TPREL_LO16; - break; - case fixup_Hexagon_TPREL_HI16: - Type = ELF::R_HEX_TPREL_HI16; - break; - case fixup_Hexagon_TPREL_32: - Type = ELF::R_HEX_TPREL_32; - break; - case fixup_Hexagon_TPREL_16: - Type = ELF::R_HEX_TPREL_16; - break; - case fixup_Hexagon_6_PCREL_X: - Type = ELF::R_HEX_6_PCREL_X; - break; - case fixup_Hexagon_GOTREL_32_6_X: - Type = ELF::R_HEX_GOTREL_32_6_X; - break; - case fixup_Hexagon_GOTREL_16_X: - Type = ELF::R_HEX_GOTREL_16_X; - break; - case fixup_Hexagon_GOTREL_11_X: - Type = ELF::R_HEX_GOTREL_11_X; - break; - case fixup_Hexagon_GOT_32_6_X: - Type = ELF::R_HEX_GOT_32_6_X; - break; - case fixup_Hexagon_GOT_16_X: - Type = ELF::R_HEX_GOT_16_X; - break; - case fixup_Hexagon_GOT_11_X: - Type = ELF::R_HEX_GOT_11_X; - break; - case fixup_Hexagon_DTPREL_32_6_X: - Type = ELF::R_HEX_DTPREL_32_6_X; - break; - case fixup_Hexagon_DTPREL_16_X: - Type = ELF::R_HEX_DTPREL_16_X; - break; - case fixup_Hexagon_DTPREL_11_X: - Type = ELF::R_HEX_DTPREL_11_X; - break; - case fixup_Hexagon_GD_GOT_32_6_X: - Type = ELF::R_HEX_GD_GOT_32_6_X; - break; - case fixup_Hexagon_GD_GOT_16_X: - Type = ELF::R_HEX_GD_GOT_16_X; - break; - case fixup_Hexagon_GD_GOT_11_X: - Type = ELF::R_HEX_GD_GOT_11_X; - break; - case fixup_Hexagon_LD_GOT_32_6_X: - Type = ELF::R_HEX_LD_GOT_32_6_X; - break; - case fixup_Hexagon_LD_GOT_16_X: - Type = ELF::R_HEX_LD_GOT_16_X; - break; - case fixup_Hexagon_LD_GOT_11_X: - Type = ELF::R_HEX_LD_GOT_11_X; - break; - case fixup_Hexagon_IE_32_6_X: - Type = ELF::R_HEX_IE_32_6_X; - break; - case fixup_Hexagon_IE_16_X: - Type = ELF::R_HEX_IE_16_X; - break; - case fixup_Hexagon_IE_GOT_32_6_X: - Type = ELF::R_HEX_IE_GOT_32_6_X; - break; - case fixup_Hexagon_IE_GOT_16_X: - Type = ELF::R_HEX_IE_GOT_16_X; - break; - case fixup_Hexagon_IE_GOT_11_X: - Type = ELF::R_HEX_IE_GOT_11_X; - break; - case fixup_Hexagon_TPREL_32_6_X: - Type = ELF::R_HEX_TPREL_32_6_X; - break; - case fixup_Hexagon_TPREL_16_X: - Type = ELF::R_HEX_TPREL_16_X; - break; - case fixup_Hexagon_TPREL_11_X: - Type = ELF::R_HEX_TPREL_11_X; - break; + switch ((unsigned)Fixup.getKind()) { + default: + DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n"); + llvm_unreachable("Unimplemented Fixup kind!"); + return ELF::R_HEX_NONE; + case FK_Data_4: + return (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32; + case FK_PCRel_4: + return ELF::R_HEX_32_PCREL; + case FK_Data_2: + return ELF::R_HEX_16; + case FK_Data_1: + return ELF::R_HEX_8; + case fixup_Hexagon_B22_PCREL: + return ELF::R_HEX_B22_PCREL; + case fixup_Hexagon_B15_PCREL: + return ELF::R_HEX_B15_PCREL; + case fixup_Hexagon_B7_PCREL: + return ELF::R_HEX_B7_PCREL; + case fixup_Hexagon_LO16: + return ELF::R_HEX_LO16; + case fixup_Hexagon_HI16: + return ELF::R_HEX_HI16; + case fixup_Hexagon_32: + return ELF::R_HEX_32; + case fixup_Hexagon_16: + return ELF::R_HEX_16; + case fixup_Hexagon_8: + return ELF::R_HEX_8; + case fixup_Hexagon_GPREL16_0: + return ELF::R_HEX_GPREL16_0; + case fixup_Hexagon_GPREL16_1: + return ELF::R_HEX_GPREL16_1; + case fixup_Hexagon_GPREL16_2: + return ELF::R_HEX_GPREL16_2; + case fixup_Hexagon_GPREL16_3: + return ELF::R_HEX_GPREL16_3; + case fixup_Hexagon_HL16: + return ELF::R_HEX_HL16; + case fixup_Hexagon_B13_PCREL: + return ELF::R_HEX_B13_PCREL; + case fixup_Hexagon_B9_PCREL: + return ELF::R_HEX_B9_PCREL; + case fixup_Hexagon_B32_PCREL_X: + return ELF::R_HEX_B32_PCREL_X; + case fixup_Hexagon_32_6_X: + return ELF::R_HEX_32_6_X; + case fixup_Hexagon_B22_PCREL_X: + return ELF::R_HEX_B22_PCREL_X; + case fixup_Hexagon_B15_PCREL_X: + return ELF::R_HEX_B15_PCREL_X; + case fixup_Hexagon_B13_PCREL_X: + return ELF::R_HEX_B13_PCREL_X; + case fixup_Hexagon_B9_PCREL_X: + return ELF::R_HEX_B9_PCREL_X; + case fixup_Hexagon_B7_PCREL_X: + return ELF::R_HEX_B7_PCREL_X; + case fixup_Hexagon_16_X: + return ELF::R_HEX_16_X; + case fixup_Hexagon_12_X: + return ELF::R_HEX_12_X; + case fixup_Hexagon_11_X: + return ELF::R_HEX_11_X; + case fixup_Hexagon_10_X: + return ELF::R_HEX_10_X; + case fixup_Hexagon_9_X: + return ELF::R_HEX_9_X; + case fixup_Hexagon_8_X: + return ELF::R_HEX_8_X; + case fixup_Hexagon_7_X: + return ELF::R_HEX_7_X; + case fixup_Hexagon_6_X: + return ELF::R_HEX_6_X; + case fixup_Hexagon_32_PCREL: + return ELF::R_HEX_32_PCREL; + case fixup_Hexagon_COPY: + return ELF::R_HEX_COPY; + case fixup_Hexagon_GLOB_DAT: + return ELF::R_HEX_GLOB_DAT; + case fixup_Hexagon_JMP_SLOT: + return ELF::R_HEX_JMP_SLOT; + case fixup_Hexagon_RELATIVE: + return ELF::R_HEX_RELATIVE; + case fixup_Hexagon_PLT_B22_PCREL: + return ELF::R_HEX_PLT_B22_PCREL; + case fixup_Hexagon_GOTREL_LO16: + return ELF::R_HEX_GOTREL_LO16; + case fixup_Hexagon_GOTREL_HI16: + return ELF::R_HEX_GOTREL_HI16; + case fixup_Hexagon_GOTREL_32: + return ELF::R_HEX_GOTREL_32; + case fixup_Hexagon_GOT_LO16: + return ELF::R_HEX_GOT_LO16; + case fixup_Hexagon_GOT_HI16: + return ELF::R_HEX_GOT_HI16; + case fixup_Hexagon_GOT_32: + return ELF::R_HEX_GOT_32; + case fixup_Hexagon_GOT_16: + return ELF::R_HEX_GOT_16; + case fixup_Hexagon_DTPMOD_32: + return ELF::R_HEX_DTPMOD_32; + case fixup_Hexagon_DTPREL_LO16: + return ELF::R_HEX_DTPREL_LO16; + case fixup_Hexagon_DTPREL_HI16: + return ELF::R_HEX_DTPREL_HI16; + case fixup_Hexagon_DTPREL_32: + return ELF::R_HEX_DTPREL_32; + case fixup_Hexagon_DTPREL_16: + return ELF::R_HEX_DTPREL_16; + case fixup_Hexagon_GD_PLT_B22_PCREL: + return ELF::R_HEX_GD_PLT_B22_PCREL; + case fixup_Hexagon_LD_PLT_B22_PCREL: + return ELF::R_HEX_LD_PLT_B22_PCREL; + case fixup_Hexagon_GD_GOT_LO16: + return ELF::R_HEX_GD_GOT_LO16; + case fixup_Hexagon_GD_GOT_HI16: + return ELF::R_HEX_GD_GOT_HI16; + case fixup_Hexagon_GD_GOT_32: + return ELF::R_HEX_GD_GOT_32; + case fixup_Hexagon_GD_GOT_16: + return ELF::R_HEX_GD_GOT_16; + case fixup_Hexagon_LD_GOT_LO16: + return ELF::R_HEX_LD_GOT_LO16; + case fixup_Hexagon_LD_GOT_HI16: + return ELF::R_HEX_LD_GOT_HI16; + case fixup_Hexagon_LD_GOT_32: + return ELF::R_HEX_LD_GOT_32; + case fixup_Hexagon_LD_GOT_16: + return ELF::R_HEX_LD_GOT_16; + case fixup_Hexagon_IE_LO16: + return ELF::R_HEX_IE_LO16; + case fixup_Hexagon_IE_HI16: + return ELF::R_HEX_IE_HI16; + case fixup_Hexagon_IE_32: + return ELF::R_HEX_IE_32; + case fixup_Hexagon_IE_GOT_LO16: + return ELF::R_HEX_IE_GOT_LO16; + case fixup_Hexagon_IE_GOT_HI16: + return ELF::R_HEX_IE_GOT_HI16; + case fixup_Hexagon_IE_GOT_32: + return ELF::R_HEX_IE_GOT_32; + case fixup_Hexagon_IE_GOT_16: + return ELF::R_HEX_IE_GOT_16; + case fixup_Hexagon_TPREL_LO16: + return ELF::R_HEX_TPREL_LO16; + case fixup_Hexagon_TPREL_HI16: + return ELF::R_HEX_TPREL_HI16; + case fixup_Hexagon_TPREL_32: + return ELF::R_HEX_TPREL_32; + case fixup_Hexagon_TPREL_16: + return ELF::R_HEX_TPREL_16; + case fixup_Hexagon_6_PCREL_X: + return ELF::R_HEX_6_PCREL_X; + case fixup_Hexagon_GOTREL_32_6_X: + return ELF::R_HEX_GOTREL_32_6_X; + case fixup_Hexagon_GOTREL_16_X: + return ELF::R_HEX_GOTREL_16_X; + case fixup_Hexagon_GOTREL_11_X: + return ELF::R_HEX_GOTREL_11_X; + case fixup_Hexagon_GOT_32_6_X: + return ELF::R_HEX_GOT_32_6_X; + case fixup_Hexagon_GOT_16_X: + return ELF::R_HEX_GOT_16_X; + case fixup_Hexagon_GOT_11_X: + return ELF::R_HEX_GOT_11_X; + case fixup_Hexagon_DTPREL_32_6_X: + return ELF::R_HEX_DTPREL_32_6_X; + case fixup_Hexagon_DTPREL_16_X: + return ELF::R_HEX_DTPREL_16_X; + case fixup_Hexagon_DTPREL_11_X: + return ELF::R_HEX_DTPREL_11_X; + case fixup_Hexagon_GD_GOT_32_6_X: + return ELF::R_HEX_GD_GOT_32_6_X; + case fixup_Hexagon_GD_GOT_16_X: + return ELF::R_HEX_GD_GOT_16_X; + case fixup_Hexagon_GD_GOT_11_X: + return ELF::R_HEX_GD_GOT_11_X; + case fixup_Hexagon_LD_GOT_32_6_X: + return ELF::R_HEX_LD_GOT_32_6_X; + case fixup_Hexagon_LD_GOT_16_X: + return ELF::R_HEX_LD_GOT_16_X; + case fixup_Hexagon_LD_GOT_11_X: + return ELF::R_HEX_LD_GOT_11_X; + case fixup_Hexagon_IE_32_6_X: + return ELF::R_HEX_IE_32_6_X; + case fixup_Hexagon_IE_16_X: + return ELF::R_HEX_IE_16_X; + case fixup_Hexagon_IE_GOT_32_6_X: + return ELF::R_HEX_IE_GOT_32_6_X; + case fixup_Hexagon_IE_GOT_16_X: + return ELF::R_HEX_IE_GOT_16_X; + case fixup_Hexagon_IE_GOT_11_X: + return ELF::R_HEX_IE_GOT_11_X; + case fixup_Hexagon_TPREL_32_6_X: + return ELF::R_HEX_TPREL_32_6_X; + case fixup_Hexagon_TPREL_16_X: + return ELF::R_HEX_TPREL_16_X; + case fixup_Hexagon_TPREL_11_X: + return ELF::R_HEX_TPREL_11_X; } - return Type; } MCObjectWriter *llvm::createHexagonELFObjectWriter(raw_pwrite_stream &OS, diff --git a/test/CodeGen/Hexagon/signed_immediates.ll b/test/CodeGen/Hexagon/signed_immediates.ll new file mode 100644 index 00000000000..a4766313cc6 --- /dev/null +++ b/test/CodeGen/Hexagon/signed_immediates.ll @@ -0,0 +1,99 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; s4_0Imm +; CHECK: memb(r0++#-1) = r1 +define i8* @foo1(i8* %a, i8 %b) { + store i8 %b, i8* %a + %c = getelementptr i8, i8* %a, i32 -1 + ret i8* %c +} + +; s4_1Imm +; CHECK: memh(r0++#-2) = r1 +define i16* @foo2(i16* %a, i16 %b) { + store i16 %b, i16* %a + %c = getelementptr i16, i16* %a, i32 -1 + ret i16* %c +} + +; s4_2Imm +; CHECK: memw(r0++#-4) = r1 +define i32* @foo3(i32* %a, i32 %b) { + store i32 %b, i32* %a + %c = getelementptr i32, i32* %a, i32 -1 + ret i32* %c +} + +; s4_3Imm +; CHECK: memd(r0++#-8) = r3:2 +define i64* @foo4(i64* %a, i64 %b) { + store i64 %b, i64* %a + %c = getelementptr i64, i64* %a, i32 -1 + ret i64* %c +} + +; s6Ext +; CHECK: if (p0.new) memw(r0+#0)=#-1 +define void @foo5(i32* %a, i1 %b) { +br i1 %b, label %x, label %y +x: + store i32 -1, i32* %a + ret void +y: + ret void +} + +; s10Ext +; CHECK: p0 = cmp.eq(r0, #-1) +define i1 @foo7(i32 %a) { + %b = icmp eq i32 %a, -1 + ret i1 %b +} + +; s11_0Ext +; CHECK: memb(r0+#-1) = r1 +define void @foo8(i8* %a, i8 %b) { + %c = getelementptr i8, i8* %a, i32 -1 + store i8 %b, i8* %c + ret void +} + +; s11_1Ext +; CHECK: memh(r0+#-2) = r1 +define void @foo9(i16* %a, i16 %b) { + %c = getelementptr i16, i16* %a, i32 -1 + store i16 %b, i16* %c + ret void +} + +; s11_2Ext +; CHECK: memw(r0+#-4) = r1 +define void @foo10(i32* %a, i32 %b) { + %c = getelementptr i32, i32* %a, i32 -1 + store i32 %b, i32* %c + ret void +} + +; s11_3Ext +; CHECK: memd(r0+#-8) = r3:2 +define void @foo11(i64* %a, i64 %b) { + %c = getelementptr i64, i64* %a, i32 -1 + store i64 %b, i64* %c + ret void +} + +; s12Ext +; CHECK: if (p0.new) r0 = #-1 +define i32 @foo12(i32 %a, i1 %b) { +br i1 %b, label %x, label %y +x: + ret i32 -1 +y: + ret i32 %a +} + +; s16Ext +; CHECK: r0 = #-2 +define i32 @foo13() { + ret i32 -2 +} \ No newline at end of file diff --git a/test/MC/Disassembler/Hexagon/alu32_alu.txt b/test/MC/Disassembler/Hexagon/alu32_alu.txt index 4dde7df0759..26b320ecde0 100644 --- a/test/MC/Disassembler/Hexagon/alu32_alu.txt +++ b/test/MC/Disassembler/Hexagon/alu32_alu.txt @@ -49,7 +49,7 @@ 0xf1 0xff 0x5f 0x78 # CHECK: r17 = #32767 0xf1 0xff 0xdf 0x78 -# CHECK: r17 = ##65535 +# CHECK: r17 = #-1 # Transfer register 0x11 0xc0 0x75 0x70 -- 2.34.1