From c2312df45cd10b580c500e1fc8f93b9693d73fe4 Mon Sep 17 00:00:00 2001 From: Misha Brukman Date: Thu, 22 May 2003 21:24:35 +0000 Subject: [PATCH] Kill `using' directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6301 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/InstrSched/InstrScheduling.cpp | 45 ++++++++-------- lib/CodeGen/InstrSched/SchedGraph.cpp | 53 +++++++++---------- .../SparcV9/InstrSched/InstrScheduling.cpp | 45 ++++++++-------- lib/Target/SparcV9/InstrSched/SchedGraph.cpp | 53 +++++++++---------- 4 files changed, 94 insertions(+), 102 deletions(-) diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index 4dae2534fde..dea628a40a6 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -14,8 +14,6 @@ #include "llvm/BasicBlock.h" #include "Support/CommandLine.h" #include -using std::cerr; -using std::vector; SchedDebugLevel_t SchedDebugLevel; @@ -64,7 +62,7 @@ private: /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT private: - vector group; + std::vector group; }; @@ -130,8 +128,8 @@ class InstrSchedule: public NonCopyable { private: const unsigned int nslots; unsigned int numInstr; - vector groups; // indexed by cycle number - vector startTime; // indexed by node id + std::vector groups; // indexed by cycle number + std::vector startTime; // indexed by node id public: // iterators typedef ScheduleIterator iterator; @@ -300,7 +298,7 @@ class DelaySlotInfo: public NonCopyable { private: const SchedGraphNode* brNode; unsigned int ndelays; - vector delayNodeVec; + std::vector delayNodeVec; cycles_t delayedNodeCycle; unsigned int delayedNodeSlotNum; @@ -314,7 +312,7 @@ public: return ndelays; } - inline const vector& getDelayNodeVec() { + inline const std::vector& getDelayNodeVec() { return delayNodeVec; } @@ -349,10 +347,11 @@ private: unsigned int totalInstrCount; cycles_t curTime; cycles_t nextEarliestIssueTime; // next cycle we can issue - vector > choicesForSlot; // indexed by slot# - vector choiceVec; // indexed by node ptr - vector numInClass; // indexed by sched class - vector nextEarliestStartTime; // indexed by opCode + // indexed by slot# + std::vector > choicesForSlot; + std::vector choiceVec; // indexed by node ptr + std::vector numInClass; // indexed by sched class + std::vector nextEarliestStartTime; // indexed by opCode hash_map delaySlotInfoForBranches; // indexed by branch node ptr @@ -987,15 +986,15 @@ ChooseOneGroup(SchedulingManager& S) { for (cycles_t c = firstCycle; c <= S.getTime(); c++) { - cerr << " Cycle " << (long)c << " : Scheduled instructions:\n"; + std::cerr << " Cycle " << (long)c <<" : Scheduled instructions:\n"; const InstrGroup* igroup = S.isched.getIGroup(c); for (unsigned int s=0; s < S.nslots; s++) { - cerr << " "; + std::cerr << " "; if ((*igroup)[s] != NULL) - cerr << * ((*igroup)[s])->getMachineInstr() << "\n"; + std::cerr << * ((*igroup)[s])->getMachineInstr() << "\n"; else - cerr << "\n"; + std::cerr << "\n"; } } } @@ -1141,7 +1140,7 @@ MarkNodeForDelaySlot(SchedulingManager& S, void FindUsefulInstructionsForDelaySlots(SchedulingManager& S, SchedGraphNode* brNode, - vector& sdelayNodeVec) + std::vector& sdelayNodeVec) { const TargetInstrInfo& mii = S.getInstrInfo(); unsigned ndelays = @@ -1155,7 +1154,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S, // Use a separate vector to hold the feasible multi-cycle nodes. // These will be used if not enough single-cycle nodes are found. // - vector mdelayNodeVec; + std::vector mdelayNodeVec; for (sg_pred_iterator P = pred_begin(brNode); P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P) @@ -1203,10 +1202,10 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S, // static void ReplaceNopsWithUsefulInstr(SchedulingManager& S, SchedGraphNode* node, - vector sdelayNodeVec, + std::vector sdelayNodeVec, SchedGraph* graph) { - vector nopNodeVec; // this will hold unused NOPs + std::vector nopNodeVec; // this will hold unused NOPs const TargetInstrInfo& mii = S.getInstrInfo(); const MachineInstr* brInstr = node->getMachineInstr(); unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode()); @@ -1287,7 +1286,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB, Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator(); MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr); - vector delayNodeVec; + std::vector delayNodeVec; const MachineInstr* brInstr = NULL; if (termInstr->getOpcode() != Instruction::Ret) @@ -1510,7 +1509,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) if (SchedDebugLevel >= Sched_PrintSchedGraphs) { - cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n"; + std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n"; graphSet.dump(); } @@ -1521,7 +1520,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) MachineBasicBlock &MBB = graph->getBasicBlock(); if (SchedDebugLevel >= Sched_PrintSchedTrace) - cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n"; + std::cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n"; // expensive! SchedPriorities schedPrio(&F, graph, getAnalysis()); @@ -1534,7 +1533,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) if (SchedDebugLevel >= Sched_PrintMachineCode) { - cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n"; + std::cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n"; MachineFunction::get(&F).dump(); } diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index 0fcb22dea9f..58fbb93c098 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -18,18 +18,15 @@ #include "Support/StringExtras.h" #include "Support/STLExtras.h" -using std::vector; -using std::pair; -using std::cerr; - //*********************** Internal Data Structures *************************/ // The following two types need to be classes, not typedefs, so we can use // opaque declarations in SchedGraph.h // -struct RefVec: public vector > { - typedef vector< pair >:: iterator iterator; - typedef vector< pair >::const_iterator const_iterator; +struct RefVec: public std::vector > { + typedef std::vector >::iterator iterator; + typedef + std::vector >::const_iterator const_iterator; }; struct RegToRefVecMap: public hash_map { @@ -126,7 +123,7 @@ SchedGraphEdge::~SchedGraphEdge() } void SchedGraphEdge::dump(int indent) const { - cerr << std::string(indent*2, ' ') << *this; + std::cerr << std::string(indent*2, ' ') << *this; } @@ -160,7 +157,7 @@ SchedGraphNode::~SchedGraphNode() } void SchedGraphNode::dump(int indent) const { - cerr << std::string(indent*2, ' ') << *this; + std::cerr << std::string(indent*2, ' ') << *this; } @@ -229,20 +226,20 @@ SchedGraph::~SchedGraph() void SchedGraph::dump() const { - cerr << " Sched Graph for Basic Block: "; - cerr << MBB.getBasicBlock()->getName() - << " (" << MBB.getBasicBlock() << ")"; + std::cerr << " Sched Graph for Basic Block: "; + std::cerr << MBB.getBasicBlock()->getName() + << " (" << MBB.getBasicBlock() << ")"; - cerr << "\n\n Actual Root nodes : "; + std::cerr << "\n\n Actual Root nodes : "; for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++) - cerr << graphRoot->outEdges[i]->getSink()->getNodeId() - << ((i == N-1)? "" : ", "); + std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId() + << ((i == N-1)? "" : ", "); - cerr << "\n Graph Nodes:\n"; + std::cerr << "\n Graph Nodes:\n"; for (const_iterator I=begin(); I != end(); ++I) - cerr << "\n" << *I->second; + std::cerr << "\n" << *I->second; - cerr << "\n"; + std::cerr << "\n"; } @@ -431,7 +428,7 @@ static const unsigned int SG_DepOrderArray[][3] = { // latency does not otherwise matter (true dependences enforce that). // void -SchedGraph::addMemEdges(const vector& memNodeVec, +SchedGraph::addMemEdges(const std::vector& memNodeVec, const TargetMachine& target) { const TargetInstrInfo& mii = target.getInstrInfo(); @@ -467,12 +464,12 @@ SchedGraph::addMemEdges(const vector& memNodeVec, // like with control dependences. // void -SchedGraph::addCallCCEdges(const vector& memNodeVec, +SchedGraph::addCallCCEdges(const std::vector& memNodeVec, MachineBasicBlock& bbMvec, const TargetMachine& target) { const TargetInstrInfo& mii = target.getInstrInfo(); - vector callNodeVec; + std::vector callNodeVec; // Find the call instruction nodes and put them in a vector. for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) @@ -671,7 +668,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, SchedGraphNode* node, - vector& memNodeVec, + std::vector& memNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { @@ -728,7 +725,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, void SchedGraph::buildNodesForBB(const TargetMachine& target, MachineBasicBlock& MBB, - vector& memNodeVec, + std::vector& memNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { @@ -761,7 +758,7 @@ SchedGraph::buildGraph(const TargetMachine& target) // We use this to add memory dependence edges without a second full walk. // // vector memVec; - vector memNodeVec; + std::vector memNodeVec; // Use this data structure to note any uses or definitions of // machine registers so we can add edges for those later without @@ -858,14 +855,14 @@ SchedGraphSet::~SchedGraphSet() void SchedGraphSet::dump() const { - cerr << "======== Sched graphs for function `" << method->getName() - << "' ========\n\n"; + std::cerr << "======== Sched graphs for function `" << method->getName() + << "' ========\n\n"; for (const_iterator I=begin(); I != end(); ++I) (*I)->dump(); - cerr << "\n====== End graphs for function `" << method->getName() - << "' ========\n\n"; + std::cerr << "\n====== End graphs for function `" << method->getName() + << "' ========\n\n"; } diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index 4dae2534fde..dea628a40a6 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -14,8 +14,6 @@ #include "llvm/BasicBlock.h" #include "Support/CommandLine.h" #include -using std::cerr; -using std::vector; SchedDebugLevel_t SchedDebugLevel; @@ -64,7 +62,7 @@ private: /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT private: - vector group; + std::vector group; }; @@ -130,8 +128,8 @@ class InstrSchedule: public NonCopyable { private: const unsigned int nslots; unsigned int numInstr; - vector groups; // indexed by cycle number - vector startTime; // indexed by node id + std::vector groups; // indexed by cycle number + std::vector startTime; // indexed by node id public: // iterators typedef ScheduleIterator iterator; @@ -300,7 +298,7 @@ class DelaySlotInfo: public NonCopyable { private: const SchedGraphNode* brNode; unsigned int ndelays; - vector delayNodeVec; + std::vector delayNodeVec; cycles_t delayedNodeCycle; unsigned int delayedNodeSlotNum; @@ -314,7 +312,7 @@ public: return ndelays; } - inline const vector& getDelayNodeVec() { + inline const std::vector& getDelayNodeVec() { return delayNodeVec; } @@ -349,10 +347,11 @@ private: unsigned int totalInstrCount; cycles_t curTime; cycles_t nextEarliestIssueTime; // next cycle we can issue - vector > choicesForSlot; // indexed by slot# - vector choiceVec; // indexed by node ptr - vector numInClass; // indexed by sched class - vector nextEarliestStartTime; // indexed by opCode + // indexed by slot# + std::vector > choicesForSlot; + std::vector choiceVec; // indexed by node ptr + std::vector numInClass; // indexed by sched class + std::vector nextEarliestStartTime; // indexed by opCode hash_map delaySlotInfoForBranches; // indexed by branch node ptr @@ -987,15 +986,15 @@ ChooseOneGroup(SchedulingManager& S) { for (cycles_t c = firstCycle; c <= S.getTime(); c++) { - cerr << " Cycle " << (long)c << " : Scheduled instructions:\n"; + std::cerr << " Cycle " << (long)c <<" : Scheduled instructions:\n"; const InstrGroup* igroup = S.isched.getIGroup(c); for (unsigned int s=0; s < S.nslots; s++) { - cerr << " "; + std::cerr << " "; if ((*igroup)[s] != NULL) - cerr << * ((*igroup)[s])->getMachineInstr() << "\n"; + std::cerr << * ((*igroup)[s])->getMachineInstr() << "\n"; else - cerr << "\n"; + std::cerr << "\n"; } } } @@ -1141,7 +1140,7 @@ MarkNodeForDelaySlot(SchedulingManager& S, void FindUsefulInstructionsForDelaySlots(SchedulingManager& S, SchedGraphNode* brNode, - vector& sdelayNodeVec) + std::vector& sdelayNodeVec) { const TargetInstrInfo& mii = S.getInstrInfo(); unsigned ndelays = @@ -1155,7 +1154,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S, // Use a separate vector to hold the feasible multi-cycle nodes. // These will be used if not enough single-cycle nodes are found. // - vector mdelayNodeVec; + std::vector mdelayNodeVec; for (sg_pred_iterator P = pred_begin(brNode); P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P) @@ -1203,10 +1202,10 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S, // static void ReplaceNopsWithUsefulInstr(SchedulingManager& S, SchedGraphNode* node, - vector sdelayNodeVec, + std::vector sdelayNodeVec, SchedGraph* graph) { - vector nopNodeVec; // this will hold unused NOPs + std::vector nopNodeVec; // this will hold unused NOPs const TargetInstrInfo& mii = S.getInstrInfo(); const MachineInstr* brInstr = node->getMachineInstr(); unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode()); @@ -1287,7 +1286,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB, Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator(); MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr); - vector delayNodeVec; + std::vector delayNodeVec; const MachineInstr* brInstr = NULL; if (termInstr->getOpcode() != Instruction::Ret) @@ -1510,7 +1509,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) if (SchedDebugLevel >= Sched_PrintSchedGraphs) { - cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n"; + std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n"; graphSet.dump(); } @@ -1521,7 +1520,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) MachineBasicBlock &MBB = graph->getBasicBlock(); if (SchedDebugLevel >= Sched_PrintSchedTrace) - cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n"; + std::cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n"; // expensive! SchedPriorities schedPrio(&F, graph, getAnalysis()); @@ -1534,7 +1533,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) if (SchedDebugLevel >= Sched_PrintMachineCode) { - cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n"; + std::cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n"; MachineFunction::get(&F).dump(); } diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index 0fcb22dea9f..58fbb93c098 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -18,18 +18,15 @@ #include "Support/StringExtras.h" #include "Support/STLExtras.h" -using std::vector; -using std::pair; -using std::cerr; - //*********************** Internal Data Structures *************************/ // The following two types need to be classes, not typedefs, so we can use // opaque declarations in SchedGraph.h // -struct RefVec: public vector > { - typedef vector< pair >:: iterator iterator; - typedef vector< pair >::const_iterator const_iterator; +struct RefVec: public std::vector > { + typedef std::vector >::iterator iterator; + typedef + std::vector >::const_iterator const_iterator; }; struct RegToRefVecMap: public hash_map { @@ -126,7 +123,7 @@ SchedGraphEdge::~SchedGraphEdge() } void SchedGraphEdge::dump(int indent) const { - cerr << std::string(indent*2, ' ') << *this; + std::cerr << std::string(indent*2, ' ') << *this; } @@ -160,7 +157,7 @@ SchedGraphNode::~SchedGraphNode() } void SchedGraphNode::dump(int indent) const { - cerr << std::string(indent*2, ' ') << *this; + std::cerr << std::string(indent*2, ' ') << *this; } @@ -229,20 +226,20 @@ SchedGraph::~SchedGraph() void SchedGraph::dump() const { - cerr << " Sched Graph for Basic Block: "; - cerr << MBB.getBasicBlock()->getName() - << " (" << MBB.getBasicBlock() << ")"; + std::cerr << " Sched Graph for Basic Block: "; + std::cerr << MBB.getBasicBlock()->getName() + << " (" << MBB.getBasicBlock() << ")"; - cerr << "\n\n Actual Root nodes : "; + std::cerr << "\n\n Actual Root nodes : "; for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++) - cerr << graphRoot->outEdges[i]->getSink()->getNodeId() - << ((i == N-1)? "" : ", "); + std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId() + << ((i == N-1)? "" : ", "); - cerr << "\n Graph Nodes:\n"; + std::cerr << "\n Graph Nodes:\n"; for (const_iterator I=begin(); I != end(); ++I) - cerr << "\n" << *I->second; + std::cerr << "\n" << *I->second; - cerr << "\n"; + std::cerr << "\n"; } @@ -431,7 +428,7 @@ static const unsigned int SG_DepOrderArray[][3] = { // latency does not otherwise matter (true dependences enforce that). // void -SchedGraph::addMemEdges(const vector& memNodeVec, +SchedGraph::addMemEdges(const std::vector& memNodeVec, const TargetMachine& target) { const TargetInstrInfo& mii = target.getInstrInfo(); @@ -467,12 +464,12 @@ SchedGraph::addMemEdges(const vector& memNodeVec, // like with control dependences. // void -SchedGraph::addCallCCEdges(const vector& memNodeVec, +SchedGraph::addCallCCEdges(const std::vector& memNodeVec, MachineBasicBlock& bbMvec, const TargetMachine& target) { const TargetInstrInfo& mii = target.getInstrInfo(); - vector callNodeVec; + std::vector callNodeVec; // Find the call instruction nodes and put them in a vector. for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) @@ -671,7 +668,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, SchedGraphNode* node, - vector& memNodeVec, + std::vector& memNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { @@ -728,7 +725,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, void SchedGraph::buildNodesForBB(const TargetMachine& target, MachineBasicBlock& MBB, - vector& memNodeVec, + std::vector& memNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { @@ -761,7 +758,7 @@ SchedGraph::buildGraph(const TargetMachine& target) // We use this to add memory dependence edges without a second full walk. // // vector memVec; - vector memNodeVec; + std::vector memNodeVec; // Use this data structure to note any uses or definitions of // machine registers so we can add edges for those later without @@ -858,14 +855,14 @@ SchedGraphSet::~SchedGraphSet() void SchedGraphSet::dump() const { - cerr << "======== Sched graphs for function `" << method->getName() - << "' ========\n\n"; + std::cerr << "======== Sched graphs for function `" << method->getName() + << "' ========\n\n"; for (const_iterator I=begin(); I != end(); ++I) (*I)->dump(); - cerr << "\n====== End graphs for function `" << method->getName() - << "' ========\n\n"; + std::cerr << "\n====== End graphs for function `" << method->getName() + << "' ========\n\n"; } -- 2.34.1