From c246b35651a419114ca48fdb73708481b35151e3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Fri, 1 Apr 2011 13:06:49 +0800 Subject: [PATCH] rk29: reset with softreset and set vcore to 1.2v for fix sdk board dead --- arch/arm/mach-rk29/clock.c | 4 +- arch/arm/mach-rk29/cpufreq.c | 4 +- arch/arm/mach-rk29/reset.c | 154 ++++++++++++++++++++++++----------- 3 files changed, 112 insertions(+), 50 deletions(-) diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c index 9b022708cf99..b776f716ec9f 100755 --- a/arch/arm/mach-rk29/clock.c +++ b/arch/arm/mach-rk29/clock.c @@ -1722,11 +1722,11 @@ void pmu_set_power_domain(enum pmu_power_domain pd, bool on) { unsigned long flags; - local_irq_save(flags); mdelay(10); + local_irq_save(flags); do_pmu_set_power_domain(pd, on); - mdelay(10); local_irq_restore(flags); + mdelay(10); } static int pd_vcodec_mode(struct clk *clk, int on) diff --git a/arch/arm/mach-rk29/cpufreq.c b/arch/arm/mach-rk29/cpufreq.c index 9c62d1c8d26b..c13a4b3b5ab1 100755 --- a/arch/arm/mach-rk29/cpufreq.c +++ b/arch/arm/mach-rk29/cpufreq.c @@ -37,9 +37,9 @@ static int no_cpufreq_access; static struct cpufreq_frequency_table freq_table[] = { // { .index = 950000, .frequency = 204000 }, // { .index = 1050000, .frequency = 300000 }, - { .index = 1150000, .frequency = 408000 }, + { .index = 1200000, .frequency = 408000 }, // { .index = 1125000, .frequency = 600000 }, - { .index = 1150000, .frequency = 816000 }, + { .index = 1200000, .frequency = 816000 }, // { .index = 1250000, .frequency = 1008000 }, // { .index = 1300000, .frequency = 1200000 }, { .frequency = CPUFREQ_TABLE_END }, diff --git a/arch/arm/mach-rk29/reset.c b/arch/arm/mach-rk29/reset.c index 03097d541f16..222c7959fb4f 100755 --- a/arch/arm/mach-rk29/reset.c +++ b/arch/arm/mach-rk29/reset.c @@ -15,46 +15,15 @@ #include #include #include -#include +#include #include #include #include -static inline void delay_500ns(void) -{ - int delay = 13; - barrier(); - while (delay--) - barrier(); -} - - -#if 0 -volatile int testflag; -static void __rk29_reset_to_maskrom(void) -{ - u32 reg; - asm("mrc p15, 0, %0, c1, c0, 0\n\t" - "bic %0, %0, #(1 << 13) @set vector to 0x00000000\n\t" - "bic %0, %0, #(1 << 0) @disable mmu\n\t" - "bic %0, %0, #(1 << 12) @disable I CACHE\n\t" - "bic %0, %0, #(1 << 2) @disable D DACHE\n\t" - "bic %0, %0, #(1 << 11) @disable \n\t" - "bic %0, %0, #(1 << 28) @disable \n\t" - "mcr p15, 0, %0, c1, c0, 0\n\t" - // "mcr p15, 0, %0, c8, c7, 0 @ invalidate whole TLB\n\t" - // "mcr p15, 0, %0, c7, c5, 6 @ invalidate BTC\n\t" - : "=r" (reg)); - - asm("b 1f\n\t" - ".align 5\n\t" - "1:\n\t" - "mcr p15, 0, %0, c7, c10, 5\n\t" - "mcr p15, 0, %0, c7, c10, 4\n\t" - "mov pc, #0" : : "r" (reg)); -} -#endif +#define LOOPS_PER_USEC 13 +#define LOOPS_PER_MSEC 12000 +#define LOOP(loops) do { int i = loops; barrier(); while (i--) barrier(); } while (0) static void pwm2gpiodefault(void) { @@ -87,8 +56,66 @@ void rb( void ) cb( uart_base ); } +static void __sramfunc __noreturn rk29_rb_with_softreset(void) +{ + u32 reg; + + asm volatile ( + "mrc p15, 0, %0, c1, c0, 0\n\t" + "bic %0, %0, #(1 << 0) @disable MMU\n\t" + "bic %0, %0, #(1 << 13) @set vector to 0x00000000\n\t" + "bic %0, %0, #(1 << 12) @disable I CACHE\n\t" + "bic %0, %0, #(1 << 2) @disable D DACHE\n\t" + "bic %0, %0, #(1 << 11) @disable Branch prediction\n\t" + "bic %0, %0, #(1 << 28) @disable TEX Remap\n\t" + "mcr p15, 0, %0, c1, c0, 0\n\t" + "mov %0, #0\n\t" + "mcr p15, 0, %0, c8, c7, 0 @invalidate whole TLB\n\t" + "mcr p15, 0, %0, c7, c5, 6 @invalidate BTC\n\t" + "dsb\n\t" + "isb\n\t" + "b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + : "=r" (reg)); + + writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON); + dsb(); + LOOP(10 * LOOPS_PER_USEC); + + writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST2_CON); + writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST1_CON); + writel(0xd9fdfdc0, RK29_CRU_PHYS + CRU_SOFTRST0_CON); + dsb(); + + LOOP(100 * LOOPS_PER_USEC); + + writel(0, RK29_CRU_PHYS + CRU_SOFTRST0_CON); + writel(0, RK29_CRU_PHYS + CRU_SOFTRST1_CON); + writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON); + dsb(); + LOOP(10 * LOOPS_PER_USEC); + writel(0, RK29_CRU_PHYS + CRU_SOFTRST2_CON); + dsb(); + LOOP(10 * LOOPS_PER_USEC); + + asm volatile ( + "b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "dsb\n\t" + "isb\n\t" + "mov pc, #0"); + + while (1); +} + void rk29_arch_reset(int mode, const char *cmd) { + void (*rb2)(void); + + rb2 = (void(*)(void))((u32)rk29_rb_with_softreset - SRAM_CODE_OFFSET + 0x10130000); + local_irq_disable(); local_fiq_disable(); @@ -101,7 +128,7 @@ void rk29_arch_reset(int mode, const char *cmd) #endif cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON); - delay_500ns(); + LOOP(LOOPS_PER_USEC); /* from panic? */ if (system_state != SYSTEM_RESTART) @@ -110,21 +137,45 @@ void rk29_arch_reset(int mode, const char *cmd) pwm2gpiodefault(); cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON); - delay_500ns(); + LOOP(LOOPS_PER_USEC); cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON); - delay_500ns(); - + LOOP(LOOPS_PER_USEC); + cru_writel(0, CRU_CLKGATE0_CON); cru_writel(0, CRU_CLKGATE1_CON); cru_writel(0, CRU_CLKGATE2_CON); cru_writel(0, CRU_CLKGATE3_CON); - delay_500ns(); + LOOP(LOOPS_PER_USEC); cru_writel(0, CRU_SOFTRST0_CON); cru_writel(0, CRU_SOFTRST1_CON); cru_writel(0, CRU_SOFTRST2_CON); - + LOOP(LOOPS_PER_USEC); + + cru_writel(1 << 16 | 1 << 13 | 1 << 11 | 1 << 1, CRU_CLKGATE3_CON); + LOOP(LOOPS_PER_USEC); + + writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_VCODEC), RK29_PMU_BASE + PMU_PD_CON); + dsb(); + while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_VCODEC)) + ; + LOOP(10 * LOOPS_PER_MSEC); + + writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_DISPLAY), RK29_PMU_BASE + PMU_PD_CON); + dsb(); + while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_DISPLAY)) + ; + LOOP(10 * LOOPS_PER_MSEC); + + writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_GPU), RK29_PMU_BASE + PMU_PD_CON); + dsb(); + while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_GPU)) + ; + LOOP(10 * LOOPS_PER_MSEC); + + cru_writel(0, CRU_CLKGATE3_CON); + LOOP(LOOPS_PER_USEC); //SPI0 clock source = periph_pll_clk, SPI0 divider=8 cru_writel((cru_readl(CRU_CLKSEL6_CON) & ~0x1FF) | (7 << 2), CRU_CLKSEL6_CON); @@ -135,17 +186,28 @@ void rk29_arch_reset(int mode, const char *cmd) //UART1 clock divider=0, UART1 clk =24MHz , UART0 and UART1 clock source=periph_pll_clk cru_writel((cru_readl(CRU_CLKSEL8_CON) & ~(7 | (0x3f << 14) | (3 << 20))) | (2 << 20), CRU_CLKSEL8_CON); + // remap bit control = 0, normal mode writel(readl(RK29_GRF_PHYS + 0xc0) & ~(1 << 21), RK29_GRF_PHYS + 0xc0); + // emmc_and_boot_en control=0, normal mode writel(readl(RK29_GRF_PHYS + 0xbc) & ~(1 << 9), RK29_GRF_PHYS + 0xbc); + dsb(); writel(0, RK29_CPU_AXI_BUS0_PHYS); writel(0, RK29_AXI1_PHYS); - - //__cpuc_flush_kern_all(); - //__cpuc_flush_user_all(); + dsb(); + + // SDMMC_CLKSRC=0, clk_source=clock divider 0 + writel(0, RK29_EMMC_PHYS + 0x0c); + // SDMMC_CTYPE=0, card_width=1 bit mode + writel(0, RK29_EMMC_PHYS + 0x18); + // SDMMC_BLKSIZ=0x200, Block size=512 + writel(0x200, RK29_EMMC_PHYS + 0x1c); + dsb(); + + __cpuc_flush_kern_all(); + __cpuc_flush_user_all(); - rb(); - + rb2(); } -- 2.34.1