From c31ecb9aaeccb64a83f25f74747aa86eee5f50bd Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 10 Feb 2004 20:55:47 +0000 Subject: [PATCH] Remove uses of MachineOperand::isVirtualRegister git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11281 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/PeepholeOptimizer.cpp | 9 ++++++--- lib/Target/X86/X86PeepholeOpt.cpp | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp index 6d07ec502a7..66508376cdc 100644 --- a/lib/Target/X86/PeepholeOptimizer.cpp +++ b/lib/Target/X86/PeepholeOptimizer.cpp @@ -191,7 +191,8 @@ namespace { MachineInstr *MI = *I; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse()) + if (MO.isRegister() && MO.isDef() && !MO.isUse() && + MRegisterInfo::isVirtualRegister(MO.getReg())) setDefinition(MO.getReg(), MI); } } @@ -250,7 +251,8 @@ namespace { /// register, return the machine instruction defining it, otherwise, return /// null. MachineInstr *getDefiningInst(MachineOperand &MO) { - if (MO.isDef() || !MO.isVirtualRegister()) return 0; + if (MO.isDef() || !MO.isRegister() || + !MRegisterInfo::isVirtualRegister(MO.getReg())) return 0; return UDC->getDefinition(MO.getReg()); } @@ -391,7 +393,8 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB, DefInst->getOpcode() == X86::MOVrr32) { // Don't propagate physical registers into PHI nodes... if (MI->getOpcode() != X86::PHI || - DefInst->getOperand(1).isVirtualRegister()) + (DefInst->getOperand(1).isRegister() && + MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg()))) Changed = Propagate(MI, i, DefInst, 1); } diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp index 6d07ec502a7..66508376cdc 100644 --- a/lib/Target/X86/X86PeepholeOpt.cpp +++ b/lib/Target/X86/X86PeepholeOpt.cpp @@ -191,7 +191,8 @@ namespace { MachineInstr *MI = *I; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse()) + if (MO.isRegister() && MO.isDef() && !MO.isUse() && + MRegisterInfo::isVirtualRegister(MO.getReg())) setDefinition(MO.getReg(), MI); } } @@ -250,7 +251,8 @@ namespace { /// register, return the machine instruction defining it, otherwise, return /// null. MachineInstr *getDefiningInst(MachineOperand &MO) { - if (MO.isDef() || !MO.isVirtualRegister()) return 0; + if (MO.isDef() || !MO.isRegister() || + !MRegisterInfo::isVirtualRegister(MO.getReg())) return 0; return UDC->getDefinition(MO.getReg()); } @@ -391,7 +393,8 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB, DefInst->getOpcode() == X86::MOVrr32) { // Don't propagate physical registers into PHI nodes... if (MI->getOpcode() != X86::PHI || - DefInst->getOperand(1).isVirtualRegister()) + (DefInst->getOperand(1).isRegister() && + MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg()))) Changed = Propagate(MI, i, DefInst, 1); } -- 2.34.1