From c3281c10c94185e18338764b225a730a7c3e3ec4 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Tue, 5 Apr 2011 22:57:07 +0000 Subject: [PATCH] A7.3 register encoding Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 10 ++++++++++ test/MC/Disassembler/ARM/invalid-VQADD-arm.txt | 10 ++++++++++ test/MC/Disassembler/ARM/neon-tests.txt | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 test/MC/Disassembler/ARM/invalid-VQADD-arm.txt diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index db76c11b7b7..58f9c1f759c 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -94,6 +94,16 @@ getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) { } // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm(). + // A7.3 register encoding + // Qd -> bit[12] == 0 + // Qn -> bit[16] == 0 + // Qm -> bit[0] == 0 + // + // If one of these bits is 1, the instruction is UNDEFINED. + if (RegClassID == ARM::QPRRegClassID && slice(RawRegister, 0, 0) == 1) { + B->SetErr(-1); + return 0; + } unsigned RegNum = RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister; diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt new file mode 100644 index 00000000000..eed012b0be6 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Qm -> bit[0] == 0, otherwise UNDEFINED +0xdb 0xe0 0x40 0xf2 diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index 39a4b241e06..2a50cc5e2f3 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -67,7 +67,7 @@ 0x5f 0xe5 0xc4 0xf2 # CHECK: vbic.i32 q2, #0xA900 -0x79 0x53 0x82 0xf3 +0x79 0x43 0x82 0xf3 # CHECK: vst2.32 {d16, d18}, [r2, :64], r2 0x92 0x9 0x42 0xf4 -- 2.34.1