From c506818b8ed538b8022cba852189e442fb55f031 Mon Sep 17 00:00:00 2001 From: hxy Date: Fri, 24 Dec 2010 17:47:50 +0800 Subject: [PATCH] add rk29 aigo board modified --- arch/arm/mach-rk29/Kconfig | 6 + arch/arm/mach-rk29/Makefile | 1 + arch/arm/mach-rk29/board-rk29-aigo.c | 1575 ++++++++++++++++++ drivers/video/display/screen/lcd_hsd100pxn.c | 10 +- 4 files changed, 1591 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rk29/board-rk29-aigo.c diff --git a/arch/arm/mach-rk29/Kconfig b/arch/arm/mach-rk29/Kconfig index ded023c1fc7a..738aa46e29e9 100644 --- a/arch/arm/mach-rk29/Kconfig +++ b/arch/arm/mach-rk29/Kconfig @@ -17,6 +17,12 @@ config MACH_RK29WINACCORD help Support for the ROCKCHIP Board For Rk29 Winaccord. +config MACH_RK29_AIGO + depends on ARCH_RK29 + bool "ROCKCHIP Board Rk29 For Aigo" + help + Support for the ROCKCHIP Board For Rk29 Aigo. + endchoice config RK29_MEM_SIZE_M diff --git a/arch/arm/mach-rk29/Makefile b/arch/arm/mach-rk29/Makefile index 4ebbd8fca798..aec43165cc40 100755 --- a/arch/arm/mach-rk29/Makefile +++ b/arch/arm/mach-rk29/Makefile @@ -2,3 +2,4 @@ obj-y += timer.o io.o devices.o iomux.o clock.o rk29-pl330.o dma.o gpio.o obj-$(CONFIG_RK29_VPU) += vpu.o vpu_mem.o obj-$(CONFIG_MACH_RK29SDK) += board-rk29sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o obj-$(CONFIG_MACH_RK29WINACCORD) += board-rk29-winaccord.o board-rk29sdk-key.o +obj-$(CONFIG_MACH_RK29_AIGO) += board-rk29-aigo.o board-rk29sdk-key.o diff --git a/arch/arm/mach-rk29/board-rk29-aigo.c b/arch/arm/mach-rk29/board-rk29-aigo.c new file mode 100644 index 000000000000..0858809a6697 --- /dev/null +++ b/arch/arm/mach-rk29/board-rk29-aigo.c @@ -0,0 +1,1575 @@ +/* arch/arm/mach-rk29/board-rk29.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include /* ddl@rock-chips.com : camera support */ +#include /* ddl@rock-chips.com : camera support */ +#include + +#include +#include + +#include +#include + +#include "devices.h" +#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h" + + +/* Set memory size of pmem */ +#ifdef CONFIG_MACH_RK29SDK_MEM_SIZE_M +#define SDRAM_SIZE (CONFIG_MACH_RK29SDK_MEM_SIZE_M * SZ_1M) +#else +#define SDRAM_SIZE SZ_512M +#endif +#define PMEM_GPU_SIZE SZ_64M +#define PMEM_UI_SIZE SZ_32M +#define PMEM_VPU_SIZE SZ_32M +#define PMEM_CAM_SIZE SZ_16M +#define MEM_FB_SIZE (3*SZ_2M) + +#define PMEM_GPU_BASE ((u32)RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE) +#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE) +#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE) +#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE) +#define MEM_FB_BASE (PMEM_CAM_BASE - MEM_FB_SIZE) +#define LINUX_SIZE (MEM_FB_BASE - RK29_SDRAM_PHYS) + +extern struct sys_timer rk29_timer; + +#define NAND_CS_MAX_NUM 1 /*form 0 to 8, it is 0 when no nand flash */ + +int rk29_nand_io_init(void) +{ +#if (NAND_CS_MAX_NUM == 2) + rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1); +#elif (NAND_CS_MAX_NUM == 3) + rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1); + rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2); +#elif (NAND_CS_MAX_NUM == 4) + rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1); + rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2); + rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3); +#elif (NAND_CS_MAX_NUM == 5) + rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1); + rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2); + rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3); + rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); +#elif (NAND_CS_MAX_NUM == 6) + rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1); + rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2); + rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3); + rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); + rk29_mux_api_set(GPIO0D6_FLASHCSN5_NAME, GPIO0H_FLASH_CSN5); +#elif (NAND_CS_MAX_NUM == 7) + rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1); + rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2); + rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3); + rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); + rk29_mux_api_set(GPIO0D6_FLASHCSN5_NAME, GPIO0H_FLASH_CSN5); + rk29_mux_api_set(GPIO0D7_FLASHCSN6_NAME, GPIO0H_FLASH_CSN6); +#elif (NAND_CS_MAX_NUM == 8) + rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1); + rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2); + rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3); + rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); + rk29_mux_api_set(GPIO0D6_FLASHCSN5_NAME, GPIO0H_FLASH_CSN5); + rk29_mux_api_set(GPIO0D7_FLASHCSN6_NAME, GPIO0H_FLASH_CSN6); + rk29_mux_api_set(GPIO1A0_FLASHCS7_MDDRTQ_NAME, GPIO1L_FLASH_CS7); +#endif + return 0; +} + +struct rk29_nand_platform_data rk29_nand_data = { + .width = 1, /* data bus width in bytes */ + .hw_ecc = 1, /* hw ecc 0: soft ecc */ + .num_flash = 1, + .io_init = rk29_nand_io_init, +}; + +static struct rk29_gpio_bank rk29_gpiobankinit[] = { + { + .id = RK29_ID_GPIO0, + .offset = RK29_GPIO0_BASE, + }, + { + .id = RK29_ID_GPIO1, + .offset = RK29_GPIO1_BASE, + }, + { + .id = RK29_ID_GPIO2, + .offset = RK29_GPIO2_BASE, + }, + { + .id = RK29_ID_GPIO3, + .offset = RK29_GPIO3_BASE, + }, + { + .id = RK29_ID_GPIO4, + .offset = RK29_GPIO4_BASE, + }, + { + .id = RK29_ID_GPIO5, + .offset = RK29_GPIO5_BASE, + }, + { + .id = RK29_ID_GPIO6, + .offset = RK29_GPIO6_BASE, + }, +}; + +#ifdef CONFIG_FB_RK29 +/***************************************************************************************** + * lcd devices + * author: zyw@rock-chips.com + *****************************************************************************************/ +//#ifdef CONFIG_LCD_TD043MGEA1 +#define LCD_TXD_PIN INVALID_GPIO +#define LCD_CLK_PIN INVALID_GPIO +#define LCD_CS_PIN INVALID_GPIO +/***************************************************************************************** +* frame buffe devices +* author: zyw@rock-chips.com +*****************************************************************************************/ +#define FB_ID 0 +#define FB_DISPLAY_ON_PIN RK29_PIN6_PD0 +#define FB_LCD_STANDBY_PIN RK29_PIN6_PD1 +#define FB_LCD_CABC_EN_PIN RK29_PIN6_PD2 +#define FB_MCU_FMK_PIN INVALID_GPIO + +#define FB_DISPLAY_ON_VALUE GPIO_HIGH +#define FB_LCD_STANDBY_VALUE GPIO_HIGH + +//#endif +static int rk29_lcd_io_init(void) +{ + int ret = 0; + return ret; +} + +static int rk29_lcd_io_deinit(void) +{ + int ret = 0; + return ret; +} + +struct rk29lcd_info rk29_lcd_info = { + .txd_pin = LCD_TXD_PIN, + .clk_pin = LCD_CLK_PIN, + .cs_pin = LCD_CS_PIN, + .io_init = rk29_lcd_io_init, + .io_deinit = rk29_lcd_io_deinit, +}; + + +static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting) +{ + int ret = 0; + if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO)) + { + ret = gpio_request(FB_MCU_FMK_PIN, NULL); + if(ret != 0) + { + gpio_free(FB_MCU_FMK_PIN); + printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n "); + } + gpio_direction_input(FB_MCU_FMK_PIN); + } + if(fb_setting->disp_on_en && (FB_DISPLAY_ON_PIN != INVALID_GPIO)) + { + ret = gpio_request(FB_DISPLAY_ON_PIN, NULL); + if(ret != 0) + { + gpio_free(FB_DISPLAY_ON_PIN); + printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n "); + } + } + + if(fb_setting->disp_on_en && (FB_LCD_STANDBY_PIN != INVALID_GPIO)) + { + ret = gpio_request(FB_LCD_STANDBY_PIN, NULL); + if(ret != 0) + { + gpio_free(FB_LCD_STANDBY_PIN); + printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n "); + } + } + + if(FB_LCD_CABC_EN_PIN != INVALID_GPIO) + { + ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL); + if(ret != 0) + { + gpio_free(FB_LCD_CABC_EN_PIN); + printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n "); + } + gpio_direction_output(FB_LCD_CABC_EN_PIN, 0); + gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW); + } + + return ret; +} + +struct rk29fb_info rk29_fb_info = { + .fb_id = FB_ID, + .disp_on_pin = FB_DISPLAY_ON_PIN, + .disp_on_value = FB_DISPLAY_ON_VALUE, + .standby_pin = FB_LCD_STANDBY_PIN, + .standby_value = FB_LCD_STANDBY_VALUE, + .mcu_fmk_pin = FB_MCU_FMK_PIN, + .lcd_info = &rk29_lcd_info, + .io_init = rk29_fb_io_init, +}; + +/* rk29 fb resource */ +struct resource rk29_fb_resource[] = { + [0] = { + .name = "lcdc reg", + .start = RK29_LCDC_PHYS, + .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "lcdc irq", + .start = IRQ_LCDC, + .end = IRQ_LCDC, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "win1 buf", + .start = MEM_FB_BASE, + .end = MEM_FB_BASE + MEM_FB_SIZE, + .flags = IORESOURCE_MEM, + }, +}; + +/*platform_device*/ +struct platform_device rk29_device_fb = { + .name = "rk29-fb", + .id = 4, + .num_resources = ARRAY_SIZE(rk29_fb_resource), + .resource = rk29_fb_resource, + .dev = { + .platform_data = &rk29_fb_info, + } +}; +#endif + +static struct android_pmem_platform_data android_pmem_pdata = { + .name = "pmem", + .start = PMEM_UI_BASE, + .size = PMEM_UI_SIZE, + .no_allocator = 0, + .cached = 1, +}; + +static struct platform_device android_pmem_device = { + .name = "android_pmem", + .id = 0, + .dev = { + .platform_data = &android_pmem_pdata, + }, +}; + + +static struct android_pmem_platform_data android_pmem_cam_pdata = { + .name = "pmem_cam", + .start = PMEM_CAM_BASE, + .size = PMEM_CAM_SIZE, + .no_allocator = 0, + .cached = 1, +}; + +static struct platform_device android_pmem_cam_device = { + .name = "android_pmem", + .id = 1, + .dev = { + .platform_data = &android_pmem_cam_pdata, + }, +}; + + +static struct vpu_mem_platform_data vpu_mem_pdata = { + .name = "vpu_mem", + .start = PMEM_VPU_BASE, + .size = PMEM_VPU_SIZE, + .cached = 1, +}; + +static struct platform_device rk29_vpu_mem_device = { + .name = "vpu_mem", + .id = 2, + .dev = { + .platform_data = &vpu_mem_pdata, + }, +}; + + +/*HANNSTAR_P1003 touch*/ +#if defined (CONFIG_HANNSTAR_P1003) +#define TOUCH_RESET_PIN RK29_PIN6_PC3 +#define TOUCH_INT_PIN RK29_PIN0_PA2 + +int p1003_init_platform_hw(void) +{ + if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){ + gpio_free(TOUCH_RESET_PIN); + printk("p1003_init_platform_hw gpio_request error\n"); + return -EIO; + } + + if(gpio_request(TOUCH_INT_PIN,NULL) != 0){ + gpio_free(TOUCH_INT_PIN); + printk("p1003_init_platform_hw gpio_request error\n"); + return -EIO; + } + gpio_pull_updown(TOUCH_INT_PIN, 1); + gpio_direction_output(TOUCH_RESET_PIN, 0); + mdelay(500); + gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW); + mdelay(500); + gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH); + + return 0; +} + + +struct p1003_platform_data p1003_info = { + .model= 1003, + .init_platform_hw= p1003_init_platform_hw, + +}; +#endif + + +/***************************************************************************************** + * i2c devices + * author: kfx@rock-chips.com +*****************************************************************************************/ +static int rk29_i2c0_io_init(void) +{ + rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL); + rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA); + return 0; +} + +static int rk29_i2c1_io_init(void) +{ + rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL); + rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA); + return 0; +} +static int rk29_i2c2_io_init(void) +{ + rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL); + rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA); + return 0; +} + +static int rk29_i2c3_io_init(void) +{ + rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL); + rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA); + return 0; +} + +struct rk29_i2c_platform_data default_i2c0_data = { + .bus_num = 0, + .flags = 0, + .slave_addr = 0xff, + .scl_rate = 400*1000, + .mode = I2C_MODE_IRQ, + .io_init = rk29_i2c0_io_init, +}; + +struct rk29_i2c_platform_data default_i2c1_data = { + .bus_num = 1, + .flags = 0, + .slave_addr = 0xff, + .scl_rate = 400*1000, + .mode = I2C_MODE_POLL, + .io_init = rk29_i2c1_io_init, +}; + +struct rk29_i2c_platform_data default_i2c2_data = { + .bus_num = 2, + .flags = 0, + .slave_addr = 0xff, + .scl_rate = 400*1000, + .mode = I2C_MODE_IRQ, + .io_init = rk29_i2c2_io_init, +}; + +struct rk29_i2c_platform_data default_i2c3_data = { + .bus_num = 3, + .flags = 0, + .slave_addr = 0xff, + .scl_rate = 400*1000, + .mode = I2C_MODE_POLL, + .io_init = rk29_i2c3_io_init, +}; + +#ifdef CONFIG_I2C0_RK29 +static struct i2c_board_info __initdata board_i2c0_devices[] = { +#if defined (CONFIG_RK1000_CONTROL) + { + .type = "rk1000_control", + .addr = 0x40, + .flags = 0, + }, +#endif +#if defined (CONFIG_SND_SOC_RK1000) + { + .type = "rk1000_i2c_codec", + .addr = 0x60, + .flags = 0, + }, +#endif +#if defined (CONFIG_SND_SOC_WM8900) + { + .type = "wm8900", + .addr = 0x1A, + .flags = 0, + }, +#endif +#if defined (CONFIG_BATTERY_STC3100) + { + .type = "stc3100", + .addr = 0x70, + .flags = 0, + }, +#endif +#if defined (CONFIG_BATTERY_BQ27510) + { + .type = "bq27510", + .addr = 0x55, + .flags = 0, + }, +#endif +#if defined (CONFIG_RTC_HYM8563) + { + .type = "rtc_hym8563", + .addr = 0x51, + .flags = 0, + ///.irq = RK2818_PIN_PA4, + }, +#endif +}; +#endif + +#ifdef CONFIG_I2C1_RK29 +static struct i2c_board_info __initdata board_i2c1_devices[] = { +#if defined (CONFIG_RK1000_CONTROL1) + { + .type = "rk1000_control", + .addr = 0x40, + .flags = 0, + }, +#endif +#if defined (CONFIG_SENSORS_AK8973) + { + .type = "ak8973", + .addr = 0x1c, + .flags = 0, + .irq = RK29_PIN4_PA1, + }, +#endif +#if defined (CONFIG_SENSORS_AK8975) + { + .type = "ak8975", + .addr = 0x1c, + .flags = 0, + .irq = RK29_PIN4_PA1, + }, +#endif +}; +#endif + +#ifdef CONFIG_I2C2_RK29 +static struct i2c_board_info __initdata board_i2c2_devices[] = { +#if defined (CONFIG_HANNSTAR_P1003) + { + .type = "p1003_touch", + .addr = 0x04, + .flags = 0, + .irq = RK29_PIN0_PA2, + .platform_data = &p1003_info, + }, +#endif +}; +#endif + +#ifdef CONFIG_I2C3_RK29 +static struct i2c_board_info __initdata board_i2c3_devices[] = { +}; +#endif + +/***************************************************************************************** + * camera devices + * author: ddl@rock-chips.com + *****************************************************************************************/ +#ifdef CONFIG_VIDEO_RK29 +#define SENSOR_NAME_0 RK29_CAM_SENSOR_NAME_OV5642 /* back camera sensor */ +#define SENSOR_IIC_ADDR_0 0x78 +#define SENSOR_IIC_ADAPTER_ID_0 1 +#define SENSOR_POWER_PIN_0 RK29_PIN6_PB7 +#define SENSOR_RESET_PIN_0 INVALID_GPIO +#define SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L +#define SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L + + +#define SENSOR_NAME_1 RK29_CAM_SENSOR_NAME_OV2659 /* front camera sensor */ +#define SENSOR_IIC_ADDR_1 0x60 +#define SENSOR_IIC_ADAPTER_ID_1 1 +#define SENSOR_POWER_PIN_1 RK29_PIN5_PD7 +#define SENSOR_RESET_PIN_1 INVALID_GPIO +#define SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L +#define SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L + +static int rk29_sensor_io_init(void); +static int rk29_sensor_io_deinit(void); + +struct rk29camera_platform_data rk29_camera_platform_data = { + .io_init = rk29_sensor_io_init, + .io_deinit = rk29_sensor_io_deinit, + .gpio_res = { + { + .gpio_reset = SENSOR_RESET_PIN_0, + .gpio_power = SENSOR_POWER_PIN_0, + .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_0|SENSOR_RESETACTIVE_LEVEL_0), + .dev_name = SENSOR_NAME_0, + }, { + .gpio_reset = SENSOR_RESET_PIN_1, + .gpio_power = SENSOR_POWER_PIN_1, + .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_1|SENSOR_RESETACTIVE_LEVEL_1), + .dev_name = SENSOR_NAME_1, + } + } +}; + +static int rk29_sensor_io_init(void) +{ + int ret = 0, i; + unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; + unsigned int camera_ioflag; + + for (i=0; i<2; i++) { + camera_reset = rk29_camera_platform_data.gpio_res[i].gpio_reset; + camera_power = rk29_camera_platform_data.gpio_res[i].gpio_power; + camera_ioflag = rk29_camera_platform_data.gpio_res[i].gpio_flag; + + if (camera_power != INVALID_GPIO) { + ret = gpio_request(camera_power, "camera power"); + if (ret) + continue; + + gpio_set_value(camera_reset, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS)); + gpio_direction_output(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS)); + + //printk("\n%s....%d %x \n",__FUNCTION__,__LINE__,(((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS)); + + } + + if (camera_reset != INVALID_GPIO) { + ret = gpio_request(camera_reset, "camera reset"); + if (ret) { + if (camera_power != INVALID_GPIO) + gpio_free(camera_power); + + continue; + } + + gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS)); + gpio_direction_output(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS)); + + //printk("\n%s....%d %x \n",__FUNCTION__,__LINE__,((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS)); + + } + } + + return 0; +} + +static int rk29_sensor_io_deinit(void) +{ + unsigned int i; + unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; + + //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); + + for (i=0; i<2; i++) { + camera_reset = rk29_camera_platform_data.gpio_res[i].gpio_reset; + camera_power = rk29_camera_platform_data.gpio_res[i].gpio_power; + + if (camera_power != INVALID_GPIO){ + gpio_direction_input(camera_power); + gpio_free(camera_power); + } + + if (camera_reset != INVALID_GPIO) { + gpio_direction_input(camera_reset); + gpio_free(camera_reset); + } + } + + return 0; +} + + +static int rk29_sensor_power(struct device *dev, int on) +{ + unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; + unsigned int camera_ioflag; + + if(rk29_camera_platform_data.gpio_res[0].dev_name && (strcmp(rk29_camera_platform_data.gpio_res[0].dev_name, dev_name(dev)) == 0)) { + camera_reset = rk29_camera_platform_data.gpio_res[0].gpio_reset; + camera_power = rk29_camera_platform_data.gpio_res[0].gpio_power; + camera_ioflag = rk29_camera_platform_data.gpio_res[0].gpio_flag; + } else if (rk29_camera_platform_data.gpio_res[1].dev_name && (strcmp(rk29_camera_platform_data.gpio_res[1].dev_name, dev_name(dev)) == 0)) { + camera_reset = rk29_camera_platform_data.gpio_res[1].gpio_reset; + camera_power = rk29_camera_platform_data.gpio_res[1].gpio_power; + camera_ioflag = rk29_camera_platform_data.gpio_res[1].gpio_flag; + } + + if (camera_reset != INVALID_GPIO) { + gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS)); + //printk("\n%s..%s..ResetPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS)); + } + if (camera_power != INVALID_GPIO) { + if (on) { + gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS)); + //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS)); + } else { + gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS)); + //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS)); + } + } + + if (camera_reset != INVALID_GPIO) { + if (on) { + msleep(3); /* delay 3 ms */ + gpio_set_value(camera_reset,(((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS)); + //printk("\n%s..%s..ResetPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_reset, (((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS)); + } + } + return 0; +} + +static struct i2c_board_info rk29_i2c_cam_info_0[] = { + { + I2C_BOARD_INFO(SENSOR_NAME_0, SENSOR_IIC_ADDR_0>>1) + }, +}; + +struct soc_camera_link rk29_iclink_0 = { + .bus_id = RK29_CAM_PLATFORM_DEV_ID, + .power = rk29_sensor_power, + .board_info = &rk29_i2c_cam_info_0[0], + .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_0, + .module_name = SENSOR_NAME_0, +}; + +/*platform_device : soc-camera need */ +struct platform_device rk29_soc_camera_pdrv_0 = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .init_name = SENSOR_NAME_0, + .platform_data = &rk29_iclink_0, + }, +}; + +static struct i2c_board_info rk29_i2c_cam_info_1[] = { + { + I2C_BOARD_INFO(SENSOR_NAME_1, SENSOR_IIC_ADDR_1>>1) + }, +}; + +struct soc_camera_link rk29_iclink_1 = { + .bus_id = RK29_CAM_PLATFORM_DEV_ID, + .power = rk29_sensor_power, + .board_info = &rk29_i2c_cam_info_1[0], + .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_1, + .module_name = SENSOR_NAME_1, +}; + +/*platform_device : soc-camera need */ +struct platform_device rk29_soc_camera_pdrv_1 = { + .name = "soc-camera-pdrv", + .id = 1, + .dev = { + .init_name = SENSOR_NAME_1, + .platform_data = &rk29_iclink_1, + }, +}; + + +extern struct platform_device rk29_device_camera; +#endif +/***************************************************************************************** + * backlight devices + * author: nzy@rock-chips.com + *****************************************************************************************/ +#ifdef CONFIG_BACKLIGHT_RK29_BL + /* + GPIO1B5_PWM0_NAME, GPIO1L_PWM0 + GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1 + GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2 + GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3 + */ + +#define PWM_ID 0 +#define PWM_MUX_NAME GPIO1B5_PWM0_NAME +#define PWM_MUX_MODE GPIO1L_PWM0 +#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5 +#define PWM_EFFECT_VALUE 1 + +//#define LCD_DISP_ON_PIN + +#ifdef LCD_DISP_ON_PIN +#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME +#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34 + +#define BL_EN_PIN GPIO0L_GPIO0A5 +#define BL_EN_VALUE GPIO_HIGH +#endif +static int rk29_backlight_io_init(void) +{ + int ret = 0; + + rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE); + #ifdef LCD_DISP_ON_PIN + rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE); + + ret = gpio_request(BL_EN_PIN, NULL); + if(ret != 0) + { + gpio_free(BL_EN_PIN); + } + + gpio_direction_output(BL_EN_PIN, 0); + gpio_set_value(BL_EN_PIN, BL_EN_VALUE); + #endif + return ret; +} + +static int rk29_backlight_io_deinit(void) +{ + int ret = 0; + #ifdef LCD_DISP_ON_PIN + gpio_free(BL_EN_PIN); + #endif + rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO); + return ret; +} +struct rk29_bl_info rk29_bl_info = { + .pwm_id = PWM_ID, + .bl_ref = PWM_EFFECT_VALUE, + .io_init = rk29_backlight_io_init, + .io_deinit = rk29_backlight_io_deinit, +}; +#endif + +/***************************************************************************************** +* pwm voltage regulator devices +******************************************************************************************/ +#if defined (CONFIG_RK29_PWM_REGULATOR) + +#define REGULATOR_PWM_ID 2 +#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME +#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2 +#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3 +#define REGULATOR_PWM_GPIO RK29_PIN2_PA3 + +static struct regulator_consumer_supply pwm_consumers[] = { + { + .supply = "vcore", + } +}; + +static struct regulator_init_data rk29_pwm_regulator_data = { + .constraints = { + .name = "PWM2", + .min_uV = 1200000, + .max_uV = 1400000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(pwm_consumers), + .consumer_supplies = pwm_consumers, +}; + +static struct pwm_platform_data rk29_regulator_pwm_platform_data = { + .pwm_id = REGULATOR_PWM_ID, + .pwm_gpio = REGULATOR_PWM_GPIO, + //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME; + .pwm_iomux_name = REGULATOR_PWM_MUX_NAME, + .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE, + .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO, + .init_data = &rk29_pwm_regulator_data, +}; + +static struct platform_device rk29_device_pwm_regulator = { + .name = "pwm-voltage-regulator", + .id = -1, + .dev = { + .platform_data = &rk29_regulator_pwm_platform_data, + }, +}; + +#endif + +/***************************************************************************************** + * SDMMC devices +*****************************************************************************************/ +#ifdef CONFIG_SDMMC0_RK29 +static int rk29_sdmmc0_cfg_gpio(void) +{ + rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD); + rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT); + rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0); + rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1); + rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2); + rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3); + rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N); + rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5); + gpio_request(RK29_PIN5_PD5,"sdmmc"); + gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH); + mdelay(100); + gpio_set_value(RK29_PIN5_PD5,GPIO_LOW); + return 0; +} + +#define CONFIG_SDMMC0_USE_DMA +struct rk29_sdmmc_platform_data default_sdmmc0_data = { + .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| + MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| + MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36), + .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), + .io_init = rk29_sdmmc0_cfg_gpio, + .dma_name = "sd_mmc", +#ifdef CONFIG_SDMMC0_USE_DMA + .use_dma = 1, +#else + .use_dma = 0, +#endif +}; +#endif +#ifdef CONFIG_SDMMC1_RK29 +#define CONFIG_SDMMC1_USE_DMA +static int rk29_sdmmc1_cfg_gpio(void) +{ + rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD); + rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT); + rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0); + rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1); + rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2); + rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3); + //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N); + return 0; +} + +#ifdef CONFIG_WIFI_CONTROL_FUNC +static int rk29sdk_wifi_status(struct device *dev); +static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id); +#endif + +#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6 + +struct rk29_sdmmc_platform_data default_sdmmc1_data = { + .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29| + MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32| + MMC_VDD_32_33|MMC_VDD_33_34), + .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ| + MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), + .io_init = rk29_sdmmc1_cfg_gpio, + .dma_name = "sdio", +#ifdef CONFIG_SDMMC1_USE_DMA + .use_dma = 1, +#else + .use_dma = 0, +#endif +#ifdef CONFIG_WIFI_CONTROL_FUNC + .status = rk29sdk_wifi_status, + .register_status_notify = rk29sdk_wifi_status_register, +#endif +#if 0 + .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N, +#endif +}; +#endif + +#ifdef CONFIG_WIFI_CONTROL_FUNC +#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6 +#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0 +#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC4 + +static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */ +static void (*wifi_status_cb)(int card_present, void *dev_id); +static void *wifi_status_cb_devid; +int rk29sdk_wifi_power_state = 0; +int rk29sdk_bt_power_state = 0; + +static int rk29sdk_wifi_status(struct device *dev) +{ + return rk29sdk_wifi_cd; +} + +static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id) +{ + if(wifi_status_cb) + return -EAGAIN; + wifi_status_cb = callback; + wifi_status_cb_devid = dev_id; + return 0; +} + +static int rk29sdk_wifi_bt_gpio_control_init(void) +{ + if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) { + pr_info("%s: request wifi_bt power gpio failed\n", __func__); + return -1; + } + + if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) { + pr_info("%s: request wifi reset gpio failed\n", __func__); + gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N); + return -1; + } + + if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) { + pr_info("%s: request bt reset gpio failed\n", __func__); + gpio_free(RK29SDK_WIFI_GPIO_RESET_N); + return -1; + } + + gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW); + gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW); + gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW); + + pr_info("%s: init finished\n",__func__); + + return 0; +} + +static int rk29sdk_wifi_power(int on) +{ + pr_info("%s: %d\n", __func__, on); + if (on){ + gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, on); + mdelay(100); + pr_info("wifi turn on power\n"); + }else{ + if (!rk29sdk_bt_power_state){ + gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, on); + mdelay(100); + pr_info("wifi shut off power\n"); + }else + { + pr_info("wifi shouldn't shut off power, bt is using it!\n"); + } + + } + + rk29sdk_wifi_power_state = on; + return 0; +} + +static int rk29sdk_wifi_reset_state; +static int rk29sdk_wifi_reset(int on) +{ + pr_info("%s: %d\n", __func__, on); + gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on); + mdelay(100); + rk29sdk_wifi_reset_state = on; + return 0; +} + +static int rk29sdk_wifi_set_carddetect(int val) +{ + pr_info("%s:%d\n", __func__, val); + rk29sdk_wifi_cd = val; + if (wifi_status_cb){ + wifi_status_cb(val, wifi_status_cb_devid); + }else { + pr_warning("%s, nobody to notify\n", __func__); + } + return 0; +} + +static struct wifi_platform_data rk29sdk_wifi_control = { + .set_power = rk29sdk_wifi_power, + .set_reset = rk29sdk_wifi_reset, + .set_carddetect = rk29sdk_wifi_set_carddetect, +}; +static struct platform_device rk29sdk_wifi_device = { + .name = "bcm4329_wlan", + .id = 1, + .dev = { + .platform_data = &rk29sdk_wifi_control, + }, +}; +#endif + +#ifdef CONFIG_VIVANTE +static struct resource resources_gpu[] = { + [0] = { + .name = "gpu_irq", + .start = IRQ_GPU, + .end = IRQ_GPU, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "gpu_base", + .start = RK29_GPU_PHYS, + .end = RK29_GPU_PHYS + RK29_GPU_PHYS_SIZE, + .flags = IORESOURCE_MEM, + }, + [2] = { + .name = "gpu_mem", + .start = PMEM_GPU_BASE, + .end = PMEM_GPU_BASE + PMEM_GPU_SIZE, + .flags = IORESOURCE_MEM, + }, +}; +struct platform_device rk29_device_gpu = { + .name = "galcore", + .id = 0, + .num_resources = ARRAY_SIZE(resources_gpu), + .resource = resources_gpu, +}; +#endif +#ifdef CONFIG_KEYS_RK29 +extern struct rk29_keys_platform_data rk29_keys_pdata; +static struct platform_device rk29_device_keys = { + .name = "rk29-keypad", + .id = -1, + .dev = { + .platform_data = &rk29_keys_pdata, + }, +}; +#endif +/********************usb*********************/ +struct usb_mass_storage_platform_data mass_storage_pdata = { + .nluns = 1, + .vendor = "RockChip", + .product = "rk9 sdk", + .release = 0x0100, +}; + +static void __init rk29_board_iomux_init(void) +{ + #ifdef CONFIG_UART0_RK29 + rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT); + rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN); + #ifdef CONFIG_UART0_CTS_RTS_RK29 + rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N); + rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N); + #endif + #endif + #ifdef CONFIG_UART1_RK29 + rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT); + rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN); + #endif + #ifdef CONFIG_UART2_RK29 + rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT); + rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN); + #ifdef CONFIG_UART2_CTS_RTS_RK29 + rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N); + rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N); + #endif + #endif + #ifdef CONFIG_UART3_RK29 + rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT); + rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN); + #ifdef CONFIG_UART3_CTS_RTS_RK29 + rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N); + rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N); + #endif + #endif + #ifdef CONFIG_SPIM0_RK29 + rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME, GPIO2H_SPI0_CLK); + rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME, GPIO2H_SPI0_CSN0); + rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME, GPIO2H_SPI0_TXD); + rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME, GPIO2H_SPI0_RXD); + #endif + #ifdef CONFIG_SPIM1_RK29 + rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK); + rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME, GPIO2H_SPI1_CSN0); + rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME, GPIO2H_SPI1_TXD); + rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME, GPIO2H_SPI1_RXD); + #endif + #ifdef CONFIG_RK29_VMAC + rk29_mux_api_set(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME, GPIO4H_RMII_CLKOUT); + rk29_mux_api_set(GPIO4C1_RMIITXEN_MIITXEN_NAME, GPIO4H_RMII_TX_EN); + rk29_mux_api_set(GPIO4C2_RMIITXD1_MIITXD1_NAME, GPIO4H_RMII_TXD1); + rk29_mux_api_set(GPIO4C3_RMIITXD0_MIITXD0_NAME, GPIO4H_RMII_TXD0); + rk29_mux_api_set(GPIO4C4_RMIIRXERR_MIIRXERR_NAME, GPIO4H_RMII_RX_ERR); + rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME, GPIO4H_RMII_CSR_DVALID); + rk29_mux_api_set(GPIO4C6_RMIIRXD1_MIIRXD1_NAME, GPIO4H_RMII_RXD1); + rk29_mux_api_set(GPIO4C7_RMIIRXD0_MIIRXD0_NAME, GPIO4H_RMII_RXD0); + + rk29_mux_api_set(GPIO0A7_MIIMDCLK_NAME, GPIO0L_MII_MDCLK); + rk29_mux_api_set(GPIO0A6_MIIMD_NAME, GPIO0L_MII_MD); + #endif + #ifdef CONFIG_RK29_PWM_REGULATOR + rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE); + #endif +} + +static struct platform_device *devices[] __initdata = { +#ifdef CONFIG_UART1_RK29 + &rk29_device_uart1, +#endif +#ifdef CONFIG_RK29_PWM_REGULATOR + &rk29_device_pwm_regulator, +#endif +#ifdef CONFIG_SPIM0_RK29 + &rk29xx_device_spi0m, +#endif +#ifdef CONFIG_SPIM1_RK29 + &rk29xx_device_spi1m, +#endif +#ifdef CONFIG_ADC_RK29 + &rk29_device_adc, +#endif +#ifdef CONFIG_I2C0_RK29 + &rk29_device_i2c0, +#endif +#ifdef CONFIG_I2C1_RK29 + &rk29_device_i2c1, +#endif +#ifdef CONFIG_I2C2_RK29 + &rk29_device_i2c2, +#endif +#ifdef CONFIG_I2C3_RK29 + &rk29_device_i2c3, +#endif + +#ifdef CONFIG_SND_RK29_SOC_I2S_2CH + &rk29_device_iis_2ch, +#endif +#ifdef CONFIG_SND_RK29_SOC_I2S_8CH + &rk29_device_iis_8ch, +#endif + +#ifdef CONFIG_KEYS_RK29 + &rk29_device_keys, +#endif +#ifdef CONFIG_SDMMC0_RK29 + &rk29_device_sdmmc0, +#endif +#ifdef CONFIG_SDMMC1_RK29 + &rk29_device_sdmmc1, +#endif + +#ifdef CONFIG_MTD_NAND_RK29XX + &rk29xx_device_nand, +#endif + +#ifdef CONFIG_WIFI_CONTROL_FUNC + &rk29sdk_wifi_device, +#endif +#ifdef CONFIG_MTD_NAND_RK29 + &rk29_device_nand, +#endif + +#ifdef CONFIG_FB_RK29 + &rk29_device_fb, +#endif +#ifdef CONFIG_BACKLIGHT_RK29_BL + &rk29_device_backlight, +#endif +#ifdef CONFIG_RK29_VMAC + &rk29_device_vmac, +#endif +#ifdef CONFIG_VIVANTE + &rk29_device_gpu, +#endif +#ifdef CONFIG_VIDEO_RK29 + &rk29_device_camera, /* ddl@rock-chips.com : camera support */ + &rk29_soc_camera_pdrv_0, + &rk29_soc_camera_pdrv_1, + &android_pmem_cam_device, +#endif + &android_pmem_device, + &rk29_vpu_mem_device, +#ifdef CONFIG_DWC_OTG + &rk29_device_dwc_otg, +#endif +#ifdef CONFIG_USB_ANDROID + &android_usb_device, + &usb_mass_storage_device, +#endif +}; + +/***************************************************************************************** + * spi devices + * author: cmc@rock-chips.com + *****************************************************************************************/ +static int rk29_vmac_register_set(void) +{ + //config rk29 vmac as rmii, 100MHz + u32 value= readl(RK29_GRF_BASE + 0xbc); + value = (value & 0xfff7ff) | (0x400); + writel(value, RK29_GRF_BASE + 0xbc); + return 0; +} + +static int rk29_rmii_io_init(void) +{ + int err; + + //set dm9161 rmii + rk29_mux_api_set(GPIO2D3_I2S0SDI_MIICOL_NAME, GPIO2H_GPIO2D3); + err = gpio_request(RK29_PIN2_PD3, "rmii"); + if (err) { + gpio_free(RK29_PIN2_PD3); + printk("-------request RK29_PIN2_PD3 fail--------\n"); + return -1; + } + gpio_direction_output(RK29_PIN2_PD3, GPIO_HIGH); + gpio_set_value(RK29_PIN2_PD3, GPIO_HIGH); + + //rmii power on + err = gpio_request(RK29_PIN6_PB0, "rmii_power_en"); + if (err) { + gpio_free(RK29_PIN6_PB0); + gpio_free(RK29_PIN2_PD3); + printk("-------request RK29_PIN6_PB0 fail--------\n"); + return -1; + } + gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH); + gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH); + + return 0; +} + +static int rk29_rmii_power_control(int enable) +{ + if (enable) { + //set dm9161 as rmii + gpio_direction_output(RK29_PIN2_PD3, GPIO_HIGH); + gpio_set_value(RK29_PIN2_PD3, GPIO_HIGH); + + //enable rmii power + gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH); + gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH); + + } + else { + gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW); + gpio_set_value(RK29_PIN6_PB0, GPIO_LOW); + } + + return 0; +} + +struct rk29_vmac_platform_data rk29_vmac_pdata = { + .vmac_register_set = rk29_vmac_register_set, + .rmii_io_init = rk29_rmii_io_init, + .rmii_power_control = rk29_rmii_power_control, +}; + +/***************************************************************************************** + * spi devices + * author: cmc@rock-chips.com + *****************************************************************************************/ +#define SPI_CHIPSELECT_NUM 2 +struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = { + { + .name = "spi0 cs0", + .cs_gpio = RK29_PIN2_PC1, + .cs_iomux_name = NULL, + }, + { + .name = "spi0 cs1", + .cs_gpio = RK29_PIN1_PA4, + .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL + .cs_iomux_mode = GPIO1L_SPI0_CSN1, + } +}; + +struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = { + { + .name = "spi1 cs0", + .cs_gpio = RK29_PIN2_PC5, + .cs_iomux_name = NULL, + }, + { + .name = "spi1 cs1", + .cs_gpio = RK29_PIN1_PA3, + .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL + .cs_iomux_mode = GPIO1L_SPI1_CSN1, + } +}; + +static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num) +{ +#if 1 + int i,j,ret; + + //cs + if (cs_gpios) { + for (i=0; inr_banks = 1; + mi->bank[0].start = RK29_SDRAM_PHYS; + mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS); + mi->bank[0].size = LINUX_SIZE; +} + +static void __init machine_rk29_mapio(void) +{ + rk29_map_common_io(); + rk29_clock_init(); + rk29_iomux_init(); +} + +MACHINE_START(RK29, "RK29board") + /* UART for LL DEBUG */ + .phys_io = RK29_UART1_PHYS, + .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc, + .boot_params = RK29_SDRAM_PHYS + 0x88000, + .fixup = machine_rk29_fixup, + .map_io = machine_rk29_mapio, + .init_irq = machine_rk29_init_irq, + .init_machine = machine_rk29_board_init, + .timer = &rk29_timer, +MACHINE_END diff --git a/drivers/video/display/screen/lcd_hsd100pxn.c b/drivers/video/display/screen/lcd_hsd100pxn.c index e75b75ef0a2a..81b3498406b3 100755 --- a/drivers/video/display/screen/lcd_hsd100pxn.c +++ b/drivers/video/display/screen/lcd_hsd100pxn.c @@ -9,7 +9,12 @@ /* Base */ #define OUT_TYPE SCREEN_RGB + +#if defined(CONFIG_MACH_RK29SDK) #define OUT_FACE OUT_D888_P666 +#elif defined(CONFIG_MACH_RK29_AIGO) +#define OUT_FACE OUT_P888 +#endif #define OUT_CLK 65000000 #define LCDC_ACLK 312000000 //29 lcdc axi DMA ƵÂÊ @@ -28,8 +33,11 @@ #define LCD_HEIGHT 152 /* Other */ #define DCLK_POL 0 +#if defined(CONFIG_MACH_RK29SDK) #define SWAP_RB 0 - +#elif defined(CONFIG_MACH_RK29_AIGO) +#define SWAP_RB 1 +#endif void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) { -- 2.34.1