From c5733ac5d31b4cac5af0bc769411386d931237ba Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 11 Mar 2008 03:14:42 +0000 Subject: [PATCH] variadic instructions don't have operand info for variadic arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48208 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 462b94bc3f4..032ef5e2d0a 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -538,6 +538,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, // the regclass is ok. const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, *II, IIOpNum); + assert((RC || II->isVariadic()) && "Expected reg class info!"); const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg); if (RC && VRC != RC) { cerr << "Register class of operand and regclass of use don't agree!\n"; @@ -604,7 +605,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, // to be able to handle it. This handles things like copies from ST(0) to // an FP vreg on x86. assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); - if (II) { + if (II && !II->isVariadic()) { assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) && "Don't have operand info for this instruction!"); } -- 2.34.1