From c5fb2b14cacaf77703c45be69596b84d14918f10 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 30 Mar 2006 00:33:26 +0000
Subject: [PATCH] Add 128-bit pmovmskb intrinsic support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27255 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/IntrinsicsX86.td |  2 ++
 lib/Target/X86/X86InstrSSE.td | 19 ++++++++++++-------
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td
index b22ea6b1e7e..522deefbd29 100644
--- a/include/llvm/IntrinsicsX86.td
+++ b/include/llvm/IntrinsicsX86.td
@@ -298,4 +298,6 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
                          llvm_v8i16_ty], [InstrNoMem]>;
   def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
               Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
+              Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [InstrNoMem]>;
 }
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 132da07a679..f1a86ada210 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -686,13 +686,6 @@ def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                               MOVHLPS_shuffle_mask)))]>;
 }
 
-def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
-                     "movmskps {$src, $dst|$dst, $src}",
-                     [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
-def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
-                     "movmskpd {$src, $dst|$dst, $src}",
-                     [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
-
 // Conversion instructions
 def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
                      "cvtpi2ps {$src, $dst|$dst, $src}", []>;
@@ -1374,6 +1367,18 @@ def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
 // Miscellaneous Instructions
 //===----------------------------------------------------------------------===//
 
+// Mask creation
+def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
+                     "movmskps {$src, $dst|$dst, $src}",
+                     [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
+def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
+                     "movmskpd {$src, $dst|$dst, $src}",
+                     [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
+
+def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
+                     "pmovmskb {$src, $dst|$dst, $src}",
+                     [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
+
 // Prefetching loads
 def PREFETCHT0   : I<0x18, MRM1m, (ops i8mem:$src),
                      "prefetcht0 $src", []>, TB,
-- 
2.34.1