From c6431eb27537a8c29f93cd9b87b9fc3aaa256f1c Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=99=88=E4=BA=AE?= Date: Thu, 14 Aug 2014 20:12:22 -0700 Subject: [PATCH] rk312x: clk_ddr enable dvfs MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: 陈亮 --- arch/arm/boot/dts/rk312x-sdk.dtsi | 2 +- arch/arm/mach-rockchip/rk312x.c | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk312x-sdk.dtsi b/arch/arm/boot/dts/rk312x-sdk.dtsi index faf62d4e75fb..199a8f4aa836 100755 --- a/arch/arm/boot/dts/rk312x-sdk.dtsi +++ b/arch/arm/boot/dts/rk312x-sdk.dtsi @@ -425,7 +425,7 @@ 528000 >; auto-freq=<0>; - status="disable"; + status="okay"; }; &pwm0 { diff --git a/arch/arm/mach-rockchip/rk312x.c b/arch/arm/mach-rockchip/rk312x.c index 591381e2106b..8643d71feffa 100755 --- a/arch/arm/mach-rockchip/rk312x.c +++ b/arch/arm/mach-rockchip/rk312x.c @@ -67,6 +67,7 @@ static struct map_desc rk312x_io_desc[] __initdata = { RK312X_DEVICE(ROM), RK312X_DEVICE(EFUSE), RK312X_DEVICE(TIMER), + RK312X_DEVICE(CPU_AXI_BUS), RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE), RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE), RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE), @@ -255,3 +256,15 @@ static int __init rk312x_pie_init(void) return 0; } arch_initcall(rk312x_pie_init); +#include "ddr_rk3126.c" +static int __init rk312x_ddr_init(void) +{ + if (cpu_is_rk312x()) { + ddr_change_freq = _ddr_change_freq; + ddr_round_rate = _ddr_round_rate; + ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh; + ddr_init(DDR3_DEFAULT, 300); + } + return 0; +} +arch_initcall_sync(rk312x_ddr_init); -- 2.34.1