From c69d99a17437d140f258bf07d6874050a9f25243 Mon Sep 17 00:00:00 2001 From: Wu Liang feng Date: Wed, 12 Oct 2016 16:12:58 +0800 Subject: [PATCH] arm64: dts: rockchip: add the 4th cell for u2phy1_otg interrupts for rk3399 The ARM GICv3 #interrupt-cells need 4 cells to encode an interrupt source. According to Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt, the 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. So we just add 0 for the 4th cell of u2phy1_otg interrupts. Change-Id: I16ff4e4296064716fe4f7ea35946085e0473f049 Signed-off-by: Wu Liang feng --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6023e7fe46f0..1d9ca4d20406 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1401,9 +1401,9 @@ u2phy1_otg: otg-port { #phy-cells = <0>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "otg-bvalid", "otg-id", "linestate"; status = "disabled"; -- 2.34.1