From c75a44cda74a20958b789d0e1980677d77f2342c Mon Sep 17 00:00:00 2001 From: Elena Demikhovsky Date: Wed, 22 Jan 2014 12:26:19 +0000 Subject: [PATCH] AVX512: combining setcc and zext is wrong on AVX512 because vector compare instruction puts result in mask register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199798 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 ++++- test/CodeGen/X86/avx512-vec-cmp.ll | 11 +++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8205feafbdf..dd67b45e728 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5082,9 +5082,12 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { if (N0.getOpcode() == ISD::SETCC) { if (!LegalOperations && VT.isVector() && N0.getValueType().getVectorElementType() == MVT::i1) { + EVT N0VT = N0.getOperand(0).getValueType(); + if (getSetCCResultType(N0VT) == N0.getValueType()) + return SDValue(); + // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. // Only do this before legalize for now. - EVT N0VT = N0.getOperand(0).getValueType(); EVT EltVT = VT.getVectorElementType(); SmallVector OneOps(VT.getVectorNumElements(), DAG.getConstant(1, EltVT)); diff --git a/test/CodeGen/X86/avx512-vec-cmp.ll b/test/CodeGen/X86/avx512-vec-cmp.ll index 822809c62ed..bc7c148d23e 100644 --- a/test/CodeGen/X86/avx512-vec-cmp.ll +++ b/test/CodeGen/X86/avx512-vec-cmp.ll @@ -122,3 +122,14 @@ define i16 @test12(<16 x i64> %a, <16 x i64> %b) nounwind { %res1 = bitcast <16 x i1> %res to i16 ret i16 %res1 } + +; CHECK-LABEL: test13 +; CHECK: vcmpeqps %zmm +; CHECK: vpbroadcastd +; CHECK: ret +define <16 x i32> @test13(<16 x float>%a, <16 x float>%b) +{ + %cmpvector_i = fcmp oeq <16 x float> %a, %b + %conv = zext <16 x i1> %cmpvector_i to <16 x i32> + ret <16 x i32> %conv +} -- 2.34.1