From c7f2036c2b2adddae8fc546c9f94f74ce2824cc8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 3 Feb 2015 11:03:43 +0000 Subject: [PATCH] [X86] Add Requires[In64BitMode] around MOVSX64rr32/MOVSX64rm32. This makes it more strictly mutexed with the ARPL instruction 32-bit mode. Helps with some disassembler changes I'm experimenting with. Should be NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227962 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrExtension.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td index eea4f17db3f..c4b2d6d3bb7 100644 --- a/lib/Target/X86/X86InstrExtension.td +++ b/lib/Target/X86/X86InstrExtension.td @@ -139,11 +139,11 @@ def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), "movs{lq|xd}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (sext GR32:$src))], IIC_MOVSX>, - Sched<[WriteALU]>; + Sched<[WriteALU]>, Requires<[In64BitMode]>; def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), "movs{lq|xd}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>, - Sched<[WriteALULd]>; + Sched<[WriteALULd]>, Requires<[In64BitMode]>; // movzbq and movzwq encodings for the disassembler def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src), -- 2.34.1