From c9ad9814771201829c448583322a479a64c20e85 Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Thu, 26 Nov 2015 15:26:10 +0000 Subject: [PATCH] [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register ARMv8.2-A adds a new ID register, ID_A64MMFR2_EL1, which behaves in the same way as ID_A64MMFR0_EL1 and ID_A64MMFR1_EL1. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15017 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254155 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/Utils/AArch64BaseInfo.cpp | 1 + lib/Target/AArch64/Utils/AArch64BaseInfo.h | 1 + test/MC/AArch64/armv8.2a-mmfr2.s | 6 ++++++ test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt | 4 ++++ 4 files changed, 12 insertions(+) create mode 100644 test/MC/AArch64/armv8.2a-mmfr2.s create mode 100644 test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp index fde50ecb7c8..1feb3380eef 100644 --- a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp +++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp @@ -192,6 +192,7 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = { {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}}, {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}}, {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}}, + {"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}}, {"mvfr0_el1", MVFR0_EL1, {}}, {"mvfr1_el1", MVFR1_EL1, {}}, {"mvfr2_el1", MVFR2_EL1, {}}, diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/lib/Target/AArch64/Utils/AArch64BaseInfo.h index 7e42f8e3601..729bcd44c31 100644 --- a/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -594,6 +594,7 @@ namespace AArch64SysReg { ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 + ID_A64MMFR2_EL1 = 0xc03a, // 11 000 0000 0111 010 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 diff --git a/test/MC/AArch64/armv8.2a-mmfr2.s b/test/MC/AArch64/armv8.2a-mmfr2.s new file mode 100644 index 00000000000..5a9b1f1f42a --- /dev/null +++ b/test/MC/AArch64/armv8.2a-mmfr2.s @@ -0,0 +1,6 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR + + mrs x3, id_aa64mmfr2_el1 +// CHECK: mrs x3, ID_AA64MMFR2_EL1 // encoding: [0x43,0x07,0x38,0xd5] +// ERROR: error: expected readable system register diff --git a/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt b/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt new file mode 100644 index 00000000000..071412672b1 --- /dev/null +++ b/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s + +[0x43,0x07,0x38,0xd5] +# CHECK: mrs x3, ID_AA64MMFR2_EL1 -- 2.34.1