From ca7481d837e81388ec3e8f94579a28fc51f0d9f4 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Mon, 17 Mar 2014 16:01:35 +0800 Subject: [PATCH] ARM: rockchip: rk3288 support msch setup --- arch/arm/boot/dts/rk3188.dtsi | 48 ++++++++----- arch/arm/boot/dts/rk3288-tb.dts | 72 +++++++++---------- arch/arm/boot/dts/rk3288.dtsi | 121 ++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/common.c | 83 +++++++++++++++++----- 4 files changed, 251 insertions(+), 73 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 3bb3256c04a0..d4acdda20927 100755 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -89,56 +89,70 @@ rockchip,aux-ctrl = <0x72000001 (~0x72000001)>; }; - cpu_axi_bus: cpu_axi_bus@10128000 { + cpu_axi_bus: cpu_axi_bus { compatible = "rockchip,cpu_axi_bus"; - reg = <0x10128000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; qos { + #address-cells = <1>; + #size-cells = <1>; + ranges; dmac { - rockchip,offset = <0x1000>; + reg = <0x10129000 0x20>; rockchip,priority = <0 0>; }; cpu0 { - rockchip,offset = <0x2000>; + reg = <0x1012a000 0x20>; rockchip,priority = <0 0>; }; - cpu1r { - rockchip,offset = <0x2080>; + cpu1_r { + reg = <0x1012a080 0x20>; rockchip,priority = <0 0>; }; - cpu1w { - rockchip,offset = <0x2100>; + cpu1_w { + reg = <0x1012a100 0x20>; rockchip,priority = <0 0>; }; peri { - rockchip,offset = <0x4000>; + reg = <0x1012c000 0x20>; rockchip,priority = <2 2>; }; gpu { - rockchip,offset = <0x5000>; + reg = <0x1012d000 0x20>; rockchip,priority = <2 1>; }; vpu { - rockchip,offset = <0x6000>; + reg = <0x1012e000 0x20>; }; vop0 { - rockchip,offset = <0x7000>; + reg = <0x1012f000 0x20>; rockchip,priority = <3 3>; }; cif0 { - rockchip,offset = <0x7080>; + reg = <0x1012f080 0x20>; }; ipp { - rockchip,offset = <0x7100>; + reg = <0x1012f100 0x20>; }; vop1 { - rockchip,offset = <0x7180>; + reg = <0x1012f180 0x20>; rockchip,priority = <3 3>; }; cif1 { - rockchip,offset = <0x7200>; + reg = <0x1012f200 0x20>; }; rga { - rockchip,offset = <0x7280>; + reg = <0x1012f280 0x20>; + }; + }; + msch { + #address-cells = <1>; + #size-cells = <1>; + ranges; + msch { + reg = <0x10128000 0x18>; + rockchip,read-latency = <0x3f>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-tb.dts b/arch/arm/boot/dts/rk3288-tb.dts index 4605b94e13eb..9d9a40286421 100755 --- a/arch/arm/boot/dts/rk3288-tb.dts +++ b/arch/arm/boot/dts/rk3288-tb.dts @@ -4,11 +4,11 @@ #include "lcd-b101ew05.dtsi" / { + fiq-debugger { + status = "okay"; + }; -fiq-debugger { - status = "okay"; - }; -backlight { + backlight { compatible = "pwm-backlight"; pwms = <&pwm0 0 25000>; brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; @@ -16,31 +16,30 @@ backlight { enable-gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>; }; -pwm_regulator { - compatible = "rockchip_pwm_regulator"; - pwms = <&pwm1 0 25000>; - rockchip,pwm_id= <1>; - rockchip,pwm_voltage_map= <925000 950000 975000 1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000 1325000 1350000 1375000 1400000>; - rockchip,pwm_voltage= <1000000>; - rockchip,pwm_min_voltage= <925000>; - rockchip,pwm_max_voltage= <1400000>; - rockchip,pwm_suspend_voltage= <950000>; - rockchip,pwm_coefficient= <475>; - regulators { - #address-cells = <1>; - #size-cells = <0>; - pwm_reg0: regulator@0{ - regulator-compatible = "pwm_dcdc1"; - regulator-name= "vdd_logic"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; + pwm_regulator { + compatible = "rockchip_pwm_regulator"; + pwms = <&pwm1 0 25000>; + rockchip,pwm_id= <1>; + rockchip,pwm_voltage_map= <925000 950000 975000 1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000 1325000 1350000 1375000 1400000>; + rockchip,pwm_voltage= <1000000>; + rockchip,pwm_min_voltage= <925000>; + rockchip,pwm_max_voltage= <1400000>; + rockchip,pwm_suspend_voltage= <950000>; + rockchip,pwm_coefficient= <475>; + regulators { + #address-cells = <1>; + #size-cells = <0>; + pwm_reg0: regulator@0 { + regulator-compatible = "pwm_dcdc1"; + regulator-name= "vdd_logic"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; }; - }; }; - codec_hdmi_i2s: codec-hdmi-i2s { compatible = "hdmi-i2s"; }; @@ -48,7 +47,7 @@ pwm_regulator { codec_hdmi_spdif: codec-hdmi-spdif { compatible = "hdmi-spdif"; }; -} +}; &i2c0 { status = "okay"; @@ -60,8 +59,8 @@ pwm_regulator { bq24296: bq24296@6b { compatible = "ti,bq24296"; reg = <0x6b>; - gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_HIGH>; - bq24296,chg_current = <1000 500 2000>; + gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_HIGH>; + bq24296,chg_current = <1000 500 2000>; status = "disable"; }; bq27320: bq27320@55 { @@ -83,7 +82,7 @@ pwm_regulator { compatible = "gs_mma8452"; reg = <0x1d>; type = ; - irq-gpio = <&gpio8 GPIO_A0 IRQ_TYPE_EDGE_FALLING>; + irq-gpio = <&gpio8 GPIO_A0 IRQ_TYPE_EDGE_FALLING>; irq_enable = <1>; poll_delay_ms = <30>; layout = <1>; @@ -92,7 +91,7 @@ pwm_regulator { compatible = "gs_lis3dh"; reg = <0x19>; type = ; - irq-gpio = <&gpio0 GPIO_A0 IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio0 GPIO_A0 IRQ_TYPE_LEVEL_LOW>; irq_enable = <1>; poll_delay_ms = <30>; layout = <1>; @@ -101,7 +100,7 @@ pwm_regulator { compatible = "ak8963"; reg = <0x0d>; type = ; - irq-gpio = <&gpio8 GPIO_A2 IRQ_TYPE_EDGE_RISING>; + irq-gpio = <&gpio8 GPIO_A2 IRQ_TYPE_EDGE_RISING>; irq_enable = <1>; poll_delay_ms = <30>; layout = <1>; @@ -111,7 +110,7 @@ pwm_regulator { compatible = "l3g20d_gyro"; reg = <0x6b>; type = ; - irq-gpio = <&gpio8 GPIO_A3 IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio8 GPIO_A3 IRQ_TYPE_LEVEL_LOW>; irq_enable = <1>; poll_delay_ms = <30>; layout = <1>; @@ -120,7 +119,7 @@ pwm_regulator { }; &i2c2 { - status = "okay"; + status = "okay"; }; &i2c3 { @@ -249,7 +248,6 @@ pwm_regulator { status = "okay"; }; - /include/ "rk808.dtsi" &rk808 { gpios =<&gpio0 GPIO_A4 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_B3 GPIO_ACTIVE_LOW>; @@ -257,7 +255,7 @@ pwm_regulator { regulators { rk808_dcdc1_reg: regulator@0{ - regulator-name= "vdd_arm"; + regulator-name= "vdd_arm"; regulator-always-on; regulator-boot-on; }; @@ -265,7 +263,7 @@ pwm_regulator { rk808_dcdc2_reg: regulator@1 { regulator-name= "vdd_gpu"; regulator-always-on; - regulator-boot-on; + regulator-boot-on; }; rk808_dcdc3_reg: regulator@2 { diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 5d6185ad4bd6..aac4549545d5 100755 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -59,6 +59,107 @@ <0xffc02000 0x1000>; }; + cpu_axi_bus: cpu_axi_bus { + compatible = "rockchip,cpu_axi_bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + qos { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* service core */ + cpup { + reg = <0xffa80000 0x20>; + }; + cpum_r { + reg = <0xffa80080 0x20>; + }; + cpum_w { + reg = <0xffa80100 0x20>; + }; + /* service dmac */ + bus_dmac { + reg = <0xffa90000 0x20>; + }; + host { + reg = <0xffa90080 0x20>; + }; + crypto { + reg = <0xffa90100 0x20>; + }; + ccp { + reg = <0xffa90180 0x20>; + }; + ccs { + reg = <0xffa90200 0x20>; + }; + /* service gpu */ + gpu_r { + reg = <0xffaa0000 0x20>; + }; + gpu_w { + reg = <0xffaa0080 0x20>; + }; + /* service peri */ + peri { + reg = <0xffab0000 0x20>; + }; + /* service vio */ + vio1_vop { + reg = <0xffad0000 0x20>; + }; + vio1_isp_w0 { + reg = <0xffad0100 0x20>; + }; + vio1_isp_w1 { + reg = <0xffad0180 0x20>; + }; + vio0_vop { + reg = <0xffad0400 0x20>; + }; + vio0_vip { + reg = <0xffad0480 0x20>; + }; + vio0_iep { + reg = <0xffad0500 0x20>; + }; + vio2_rga_r { + reg = <0xffad0800 0x20>; + }; + vio2_rga_w { + reg = <0xffad0880 0x20>; + }; + vio1_isp_r { + reg = <0xffad0900 0x20>; + }; + /* service video */ + video { + reg = <0xffae0000 0x20>; + }; + /* service hevc */ + hevc_r { + reg = <0xffaf0000 0x20>; + }; + hevc_w { + reg = <0xffaf0080 0x20>; + }; + }; + msch { + #address-cells = <1>; + #size-cells = <1>; + ranges; + msch@0 { + reg = <0xffac0000 0x40>; + rockchip,read-latency = <0xff>; + }; + msch@1 { + reg = <0xffac0080 0x40>; + rockchip,read-latency = <0xff>; + }; + }; + }; + sram: sram@ff710000 { compatible = "mmio-sram"; reg = <0xff710000 0x8000>; /* 32k */ @@ -302,6 +403,26 @@ // pinctrl-0 = <&spdif_tx>; }; + pwm0: pwm@ff680000 { + reg = <0xff680000 0x10>; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + reg = <0xff680010 0x10>; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + reg = <0xff680020 0x10>; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + reg = <0xff680030 0x10>; + status = "disabled"; + }; + ion { compatible = "rockchip,ion"; #address-cells = <1>; diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c index 14dfcf710595..a9fea3dab329 100755 --- a/arch/arm/mach-rockchip/common.c +++ b/arch/arm/mach-rockchip/common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include "cpu_axi.h" @@ -29,47 +30,88 @@ static int __init rockchip_cpu_axi_init(void) { - struct device_node *np, *cp; - void __iomem *base, *cbase; + struct device_node *np, *gp, *cp; + void __iomem *base; np = of_find_compatible_node(NULL, NULL, "rockchip,cpu_axi_bus"); if (!np) return -ENODEV; - base = of_iomap(np, 0); - - np = of_get_child_by_name(np, "qos"); - if (np) { - for_each_child_of_node(np, cp) { - u32 offset, priority[2], mode, bandwidth, saturation; - if (of_property_read_u32(cp, "rockchip,offset", &offset)) - continue; - pr_debug("qos: %s offset %x\n", cp->name, offset); - cbase = base + offset; + gp = of_get_child_by_name(np, "qos"); + if (gp) { + for_each_child_of_node(gp, cp) { + u32 priority[2], mode, bandwidth, saturation; + base = NULL; +#ifdef DEBUG + { + struct resource r; + of_address_to_resource(cp, 0, &r); + pr_debug("qos: %s [%x ~ %x]\n", cp->name, r.start, r.end); + } +#endif if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) { - CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], cbase); + if (!base) + base = of_iomap(cp, 0); + if (!base) + continue; + CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], base); pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]); } if (!of_property_read_u32(cp, "rockchip,mode", &mode)) { - CPU_AXI_SET_QOS_MODE(mode, cbase); + if (!base) + base = of_iomap(cp, 0); + if (!base) + continue; + CPU_AXI_SET_QOS_MODE(mode, base); pr_debug("qos: %s mode %x\n", cp->name, mode); } if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) { - CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, cbase); + if (!base) + base = of_iomap(cp, 0); + if (!base) + continue; + CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base); pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth); } if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) { - CPU_AXI_SET_QOS_SATURATION(saturation, cbase); + if (!base) + base = of_iomap(cp, 0); + if (!base) + continue; + CPU_AXI_SET_QOS_SATURATION(saturation, base); pr_debug("qos: %s saturation %x\n", cp->name, saturation); } + if (base) + iounmap(base); } }; - writel_relaxed(0x3f, base + 0x0014); // memory scheduler read latency + gp = of_get_child_by_name(np, "msch"); + if (gp) { + for_each_child_of_node(gp, cp) { + u32 val; + base = NULL; +#ifdef DEBUG + { + struct resource r; + of_address_to_resource(cp, 0, &r); + pr_debug("msch: %s [%x ~ %x]\n", cp->name, r.start, r.end); + } +#endif + if (!of_property_read_u32(cp, "rockchip,read-latency", &val)) { + if (!base) + base = of_iomap(cp, 0); + if (!base) + continue; + writel_relaxed(val, base + 0x0014); // memory scheduler read latency + pr_debug("msch: %s read latency %x\n", cp->name, val); + } + if (base) + iounmap(base); + } + } dsb(); - iounmap(base); - return 0; } early_initcall(rockchip_cpu_axi_init); @@ -80,6 +122,9 @@ static int __init rockchip_pl330_l2_cache_init(void) void __iomem *base; u32 aux[2] = { 0, ~0 }, prefetch, power; + if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9) + return -ENODEV; + np = of_find_compatible_node(NULL, NULL, "rockchip,pl310-cache"); if (!np) return -ENODEV; -- 2.34.1