From cbec3b00bd70a29d1451f4d87579840b1560e87e Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Fri, 19 Aug 2005 18:50:46 +0000
Subject: [PATCH] Put register classes in namespaces

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22924 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Alpha/AlphaRegisterInfo.td | 4 ++--
 lib/Target/IA64/IA64RegisterInfo.td   | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.td b/lib/Target/Alpha/AlphaRegisterInfo.td
index a5bbd2807ae..e1fb2352a23 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.td
+++ b/lib/Target/Alpha/AlphaRegisterInfo.td
@@ -79,7 +79,7 @@ def F30 : FPR<30, "$f30">;  def F31 : FPR<31, "$f31">;
 
 /// Register classes
 // Don't allocate 15, 28, 30, 31
-def GPRC : RegisterClass<i64, 64,
+def GPRC : RegisterClass<"Alpha", i64, 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
       R23, R24, R25, 
@@ -93,7 +93,7 @@ def GPRC : RegisterClass<i64, 64,
 
 // Don't allocate 15, 29, 30, 31
 // Allocation volatiles only for now
-def FPRC : RegisterClass<f64, 64, [F0, F1, 
+def FPRC : RegisterClass<"Alpha", f64, 64, [F0, F1, 
         F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
         F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
         // Saved:
diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td
index 9d33dc30558..bb58f175a47 100644
--- a/lib/Target/IA64/IA64RegisterInfo.td
+++ b/lib/Target/IA64/IA64RegisterInfo.td
@@ -233,7 +233,7 @@ def B6 : GR<0, "b6">;
 // FIXME/XXX  we also reserve r22 for calculating addresses
 // in IA64RegisterInfo.cpp
 
-def GR : RegisterClass<i64, 64, 
+def GR : RegisterClass<"IA64", i64, 64, 
        [
        
 //FIXME!: for readability, we don't want the out registers to be the first
@@ -279,7 +279,7 @@ def GR : RegisterClass<i64, 64,
 
 // these are the scratch (+stacked) FP registers
 // ZERO (F0) and ONE (F1) are not here
-def FP : RegisterClass<f64, 64, 
+def FP : RegisterClass<"IA64", f64, 64, 
        [F6, F7, 
 	F8, F9, F10, F11, F12, F13, F14, F15, 
 	F32, F33, F34, F35, F36, F37, F38, F39, 
@@ -296,7 +296,7 @@ def FP : RegisterClass<f64, 64,
 	F120, F121, F122, F123, F124, F125, F126, F127]>;
 
 // these are the predicate registers, p0 (1/TRUE) is not here
-def PR : RegisterClass<i1, 64, 
+def PR : RegisterClass<"IA64", i1, 64, 
 
 // for now, let's be wimps and only have the scratch predicate regs
  [p6, p7, p8, p9, p10, p11, p12, p13, p14, p15]> {
-- 
2.34.1