From cc96ac3a7d1513e48c452f11d39ff00ecc8820fe Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 20 Sep 2006 03:59:25 +0000 Subject: [PATCH] Add a note that we should match rlwnm better git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30508 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/README.txt | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt index b0840a5e501..cfc7eb38b28 100644 --- a/lib/Target/PowerPC/README.txt +++ b/lib/Target/PowerPC/README.txt @@ -6,6 +6,40 @@ TODO: ===-------------------------------------------------------------------------=== +We only produce the rlwnm instruction for rotate instructions. We should +at least match stuff like: + +unsigned rot_and(unsigned X, int Y) { + unsigned T = (X << Y) | (X >> (32-Y)); + T &= 127; + return T; +} + +_foo3: + rlwnm r2, r3, r4, 0, 31 + rlwinm r3, r2, 0, 25, 31 + blr + +... which is the basic pattern that should be written in the instr. It may +also be useful for stuff like: + +long long foo2(long long X, int C) { + return X << (C&~32); +} + +which currently produces: + +_foo2: + rlwinm r2, r5, 0, 27, 25 + subfic r5, r2, 32 + slw r3, r3, r2 + srw r5, r4, r5 + or r3, r3, r5 + slw r4, r4, r2 + blr + +===-------------------------------------------------------------------------=== + Support 'update' load/store instructions. These are cracked on the G5, but are still a codesize win. -- 2.34.1