From cd3ff7acecce861765cfc711a608d84fbecc785f Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Fri, 3 Dec 2010 21:45:14 +0800 Subject: [PATCH] rk29: clock: add sdmmc_ahb gate --- arch/arm/mach-rk29/clock.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c index 89382ce1b676..324b9770e3d6 100755 --- a/arch/arm/mach-rk29/clock.c +++ b/arch/arm/mach-rk29/clock.c @@ -869,6 +869,27 @@ static struct clk clk_emmc = { .clksel_shift = 18, }; +static struct clk clk_sdmmc0_ahb = { + .name = "sdmmc0_ahb", + .parent = &hclk_periph, + .mode = gate_mode, + .gate_idx = CLK_GATE_SDMMC0_AHB, +}; + +static struct clk clk_sdmmc1_ahb = { + .name = "sdmmc1_ahb", + .parent = &hclk_periph, + .mode = gate_mode, + .gate_idx = CLK_GATE_SDMMC1_AHB, +}; + +static struct clk clk_emmc_ahb = { + .name = "emmc_ahb", + .parent = &hclk_periph, + .mode = gate_mode, + .gate_idx = CLK_GATE_EMMC_AHB, +}; + static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &periph_pll_clk, &codec_pll_clk, &arm_pll_clk }; @@ -1439,8 +1460,11 @@ static struct clk_lookup clks[] = { CLK1(sdmmc_src), CLK("rk29_sdmmc.0", "sdmmc", &clk_sdmmc0), + CLK("rk29_sdmmc.0", "sdmmc_ahb", &clk_sdmmc0_ahb), CLK("rk29_sdmmc.1", "sdmmc", &clk_sdmmc1), + CLK("rk29_sdmmc.1", "sdmmc_ahb", &clk_sdmmc1_ahb), CLK1(emmc), + CLK1(emmc_ahb), CLK1(ddr), CLK1(uart01_src), -- 2.34.1