From cf125d02a08b0bde90739425da7c4af9ea43b9d7 Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Sat, 12 Jun 2010 01:53:48 +0000 Subject: [PATCH] More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrSSE.td | 16 +++++++++++++ test/MC/AsmParser/X86/x86_32-encoding.s | 32 +++++++++++++++++++++++++ test/MC/AsmParser/X86/x86_64-encoding.s | 32 +++++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 945d69f9e26..867536d5315 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -768,6 +768,22 @@ multiclass basic_sse12_fp_binop_rm opc, string OpcodeStr, !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>; + def V#NAME#PSrm : VPSI { + let Constraints = ""; + let isAsmParserOnly = 1; + } + + def V#NAME#PDrm : VPDI { + let Constraints = ""; + let isAsmParserOnly = 1; + } + // Intrinsic operation, reg+reg. def SSrr_Int : SSI