From d0f99639c16ddad697db30e75643ae4cc52c3e80 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Thu, 15 Aug 2013 13:45:36 +0000 Subject: [PATCH] [Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/Intrinsics.td | 1 + include/llvm/IR/IntrinsicsMips.td | 207 +++++++++ lib/Target/Mips/MipsMSAInstrInfo.td | 467 ++++++++++++++++++++ test/CodeGen/Mips/msa/2rf.ll | 192 +++++++++ test/CodeGen/Mips/msa/2rf_exup.ll | 78 ++++ test/CodeGen/Mips/msa/2rf_float_int.ll | 78 ++++ test/CodeGen/Mips/msa/2rf_fq.ll | 78 ++++ test/CodeGen/Mips/msa/2rf_int_float.ll | 116 +++++ test/CodeGen/Mips/msa/2rf_tq.ll | 46 ++ test/CodeGen/Mips/msa/3rf.ll | 354 +++++++++++++++ test/CodeGen/Mips/msa/3rf_4rf.ll | 102 +++++ test/CodeGen/Mips/msa/3rf_exdo.ll | 46 ++ test/CodeGen/Mips/msa/3rf_float_int.ll | 46 ++ test/CodeGen/Mips/msa/3rf_int_float.ll | 574 +++++++++++++++++++++++++ 14 files changed, 2385 insertions(+) create mode 100644 test/CodeGen/Mips/msa/2rf.ll create mode 100644 test/CodeGen/Mips/msa/2rf_exup.ll create mode 100644 test/CodeGen/Mips/msa/2rf_float_int.ll create mode 100644 test/CodeGen/Mips/msa/2rf_fq.ll create mode 100644 test/CodeGen/Mips/msa/2rf_int_float.ll create mode 100644 test/CodeGen/Mips/msa/2rf_tq.ll create mode 100644 test/CodeGen/Mips/msa/3rf.ll create mode 100644 test/CodeGen/Mips/msa/3rf_4rf.ll create mode 100644 test/CodeGen/Mips/msa/3rf_exdo.ll create mode 100644 test/CodeGen/Mips/msa/3rf_float_int.ll create mode 100644 test/CodeGen/Mips/msa/3rf_int_float.ll diff --git a/include/llvm/IR/Intrinsics.td b/include/llvm/IR/Intrinsics.td index 18f56d2e150..856e0a5824d 100644 --- a/include/llvm/IR/Intrinsics.td +++ b/include/llvm/IR/Intrinsics.td @@ -165,6 +165,7 @@ def llvm_v4i64_ty : LLVMType; // 4 x i64 def llvm_v8i64_ty : LLVMType; // 8 x i64 def llvm_v16i64_ty : LLVMType; // 16 x i64 +def llvm_v8f16_ty : LLVMType; // 8 x half (__fp16) def llvm_v2f32_ty : LLVMType; // 2 x float def llvm_v4f32_ty : LLVMType; // 4 x float def llvm_v8f32_ty : LLVMType; // 8 x float diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td index f497c73a73b..f49995e0eb1 100644 --- a/include/llvm/IR/IntrinsicsMips.td +++ b/include/llvm/IR/IntrinsicsMips.td @@ -777,6 +777,213 @@ def int_mips_dpsub_u_w : GCCBuiltin<"__builtin_msa_dpsub_u_w">, def int_mips_dpsub_u_d : GCCBuiltin<"__builtin_msa_dpsub_u_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty], []>; +def int_mips_fadd_w : GCCBuiltin<"__builtin_msa_fadd_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fadd_d : GCCBuiltin<"__builtin_msa_fadd_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fceq_w : GCCBuiltin<"__builtin_msa_fceq_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fceq_d : GCCBuiltin<"__builtin_msa_fceq_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fcle_w : GCCBuiltin<"__builtin_msa_fcle_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fcle_d : GCCBuiltin<"__builtin_msa_fcle_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fclt_w : GCCBuiltin<"__builtin_msa_fclt_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fclt_d : GCCBuiltin<"__builtin_msa_fclt_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fclass_w : GCCBuiltin<"__builtin_msa_fclass_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], []>; +def int_mips_fclass_d : GCCBuiltin<"__builtin_msa_fclass_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], []>; + +def int_mips_fcge_w : GCCBuiltin<"__builtin_msa_fcge_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fcge_d : GCCBuiltin<"__builtin_msa_fcge_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fcgt_w : GCCBuiltin<"__builtin_msa_fcgt_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fcgt_d : GCCBuiltin<"__builtin_msa_fcgt_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fcne_w : GCCBuiltin<"__builtin_msa_fcne_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fcne_d : GCCBuiltin<"__builtin_msa_fcne_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fcun_w : GCCBuiltin<"__builtin_msa_fcun_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fcun_d : GCCBuiltin<"__builtin_msa_fcun_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fdiv_w : GCCBuiltin<"__builtin_msa_fdiv_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fdiv_d : GCCBuiltin<"__builtin_msa_fdiv_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fexdo_h : GCCBuiltin<"__builtin_msa_fexdo_h">, + Intrinsic<[llvm_v8f16_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fexdo_w : GCCBuiltin<"__builtin_msa_fexdo_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fexp2_w : GCCBuiltin<"__builtin_msa_fexp2_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4i32_ty], []>; +def int_mips_fexp2_d : GCCBuiltin<"__builtin_msa_fexp2_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2i64_ty], []>; + +def int_mips_fexupl_w : GCCBuiltin<"__builtin_msa_fexupl_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v8f16_ty], []>; +def int_mips_fexupl_d : GCCBuiltin<"__builtin_msa_fexupl_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty], []>; + +def int_mips_fexupr_w : GCCBuiltin<"__builtin_msa_fexupr_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v8f16_ty], []>; +def int_mips_fexupr_d : GCCBuiltin<"__builtin_msa_fexupr_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty], []>; + +def int_mips_ffint_s_w : GCCBuiltin<"__builtin_msa_ffint_s_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], []>; +def int_mips_ffint_s_d : GCCBuiltin<"__builtin_msa_ffint_s_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2i64_ty], []>; + +def int_mips_ffint_u_w : GCCBuiltin<"__builtin_msa_ffint_u_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], []>; +def int_mips_ffint_u_d : GCCBuiltin<"__builtin_msa_ffint_u_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2i64_ty], []>; + +def int_mips_ffql_w : GCCBuiltin<"__builtin_msa_ffql_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], []>; +def int_mips_ffql_d : GCCBuiltin<"__builtin_msa_ffql_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], []>; + +def int_mips_ffqr_w : GCCBuiltin<"__builtin_msa_ffqr_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], []>; +def int_mips_ffqr_d : GCCBuiltin<"__builtin_msa_ffqr_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], []>; + +def int_mips_fill_b : GCCBuiltin<"__builtin_msa_fill_b">, + Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty], []>; +def int_mips_fill_h : GCCBuiltin<"__builtin_msa_fill_h">, + Intrinsic<[llvm_v8i16_ty], [llvm_i32_ty], []>; +def int_mips_fill_w : GCCBuiltin<"__builtin_msa_fill_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_i32_ty], []>; + +def int_mips_flog2_w : GCCBuiltin<"__builtin_msa_flog2_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>; +def int_mips_flog2_d : GCCBuiltin<"__builtin_msa_flog2_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], []>; + +def int_mips_fmadd_w : GCCBuiltin<"__builtin_msa_fmadd_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fmadd_d : GCCBuiltin<"__builtin_msa_fmadd_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fmax_w : GCCBuiltin<"__builtin_msa_fmax_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fmax_d : GCCBuiltin<"__builtin_msa_fmax_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fmax_a_w : GCCBuiltin<"__builtin_msa_fmax_a_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fmax_a_d : GCCBuiltin<"__builtin_msa_fmax_a_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fmin_w : GCCBuiltin<"__builtin_msa_fmin_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fmin_d : GCCBuiltin<"__builtin_msa_fmin_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fmin_a_w : GCCBuiltin<"__builtin_msa_fmin_a_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fmin_a_d : GCCBuiltin<"__builtin_msa_fmin_a_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fmsub_w : GCCBuiltin<"__builtin_msa_fmsub_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fmsub_d : GCCBuiltin<"__builtin_msa_fmsub_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fmul_w : GCCBuiltin<"__builtin_msa_fmul_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fmul_d : GCCBuiltin<"__builtin_msa_fmul_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_frint_w : GCCBuiltin<"__builtin_msa_frint_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>; +def int_mips_frint_d : GCCBuiltin<"__builtin_msa_frint_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], []>; + +def int_mips_frcp_w : GCCBuiltin<"__builtin_msa_frcp_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>; +def int_mips_frcp_d : GCCBuiltin<"__builtin_msa_frcp_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], []>; + +def int_mips_frsqrt_w : GCCBuiltin<"__builtin_msa_frsqrt_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>; +def int_mips_frsqrt_d : GCCBuiltin<"__builtin_msa_frsqrt_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], []>; + +def int_mips_fseq_w : GCCBuiltin<"__builtin_msa_fseq_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fseq_d : GCCBuiltin<"__builtin_msa_fseq_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fsle_w : GCCBuiltin<"__builtin_msa_fsle_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fsle_d : GCCBuiltin<"__builtin_msa_fsle_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fslt_w : GCCBuiltin<"__builtin_msa_fslt_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fslt_d : GCCBuiltin<"__builtin_msa_fslt_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fsge_w : GCCBuiltin<"__builtin_msa_fsge_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fsge_d : GCCBuiltin<"__builtin_msa_fsge_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fsgt_w : GCCBuiltin<"__builtin_msa_fsgt_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fsgt_d : GCCBuiltin<"__builtin_msa_fsgt_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fsne_w : GCCBuiltin<"__builtin_msa_fsne_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fsne_d : GCCBuiltin<"__builtin_msa_fsne_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_fsqrt_w : GCCBuiltin<"__builtin_msa_fsqrt_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>; +def int_mips_fsqrt_d : GCCBuiltin<"__builtin_msa_fsqrt_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], []>; + +def int_mips_fsub_w : GCCBuiltin<"__builtin_msa_fsub_w">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_fsub_d : GCCBuiltin<"__builtin_msa_fsub_d">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + +def int_mips_ftint_s_w : GCCBuiltin<"__builtin_msa_ftint_s_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], []>; +def int_mips_ftint_s_d : GCCBuiltin<"__builtin_msa_ftint_s_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], []>; + +def int_mips_ftint_u_w : GCCBuiltin<"__builtin_msa_ftint_u_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], []>; +def int_mips_ftint_u_d : GCCBuiltin<"__builtin_msa_ftint_u_d">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], []>; + +def int_mips_ftq_h : GCCBuiltin<"__builtin_msa_ftq_h">, + Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; +def int_mips_ftq_w : GCCBuiltin<"__builtin_msa_ftq_w">, + Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>; + def int_mips_ilvev_b : GCCBuiltin<"__builtin_msa_ilvev_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; def int_mips_ilvev_h : GCCBuiltin<"__builtin_msa_ilvev_h">, diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index ea8938b8dcc..82db5681487 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -247,6 +247,130 @@ class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; +class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; +class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; + +class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; +class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; + +class FCGE_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; +class FCGE_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; + +class FCGT_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; +class FCGT_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; + +class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; +class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; + +class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; +class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; + +class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; +class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; + +class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; +class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; + +class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; +class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; + +class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; +class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; + +class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; +class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; + +class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; +class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; + +class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; +class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; + +class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; +class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; + +class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; +class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; + +class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; +class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; + +class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; +class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; + +class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; +class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; + +class FILL_B_ENC : MSA_2R_FMT<0b11000000, 0b00, 0b011110>; +class FILL_H_ENC : MSA_2R_FMT<0b11000000, 0b01, 0b011110>; +class FILL_W_ENC : MSA_2R_FMT<0b11000000, 0b10, 0b011110>; + +class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; +class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; + +class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; +class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; + +class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; +class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; + +class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; +class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; + +class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; +class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; + +class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; +class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; + +class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; +class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; + +class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; +class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; + +class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; +class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; + +class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; +class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; + +class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; +class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; + +class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; +class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; + +class FSGE_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; +class FSGE_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; + +class FSGT_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; +class FSGT_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; + +class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; +class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; + +class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; +class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; + +class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; +class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; + +class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; +class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; + +class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; +class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; + +class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; +class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; + +class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; +class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; + +class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; +class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; + class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; @@ -849,6 +973,221 @@ class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, NoItinerary, MSA128, MSA128>; +class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", int_mips_fadd_w, + NoItinerary, MSA128, MSA128>, + IsCommutable; +class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", int_mips_fadd_d, + NoItinerary, MSA128, MSA128>, + IsCommutable; + +class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", int_mips_fceq_w, + NoItinerary, MSA128, MSA128>, + IsCommutable; +class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", int_mips_fceq_d, + NoItinerary, MSA128, MSA128>, + IsCommutable; + +class FCGE_W_DESC : MSA_3RF_DESC_BASE<"fcge.w", int_mips_fcge_w, + NoItinerary, MSA128, MSA128>; +class FCGE_D_DESC : MSA_3RF_DESC_BASE<"fcge.d", int_mips_fcge_d, + NoItinerary, MSA128, MSA128>; + +class FCGT_W_DESC : MSA_3RF_DESC_BASE<"fcgt.w", int_mips_fcgt_w, + NoItinerary, MSA128, MSA128>; +class FCGT_D_DESC : MSA_3RF_DESC_BASE<"fcgt.d", int_mips_fcgt_d, + NoItinerary, MSA128, MSA128>; + +class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, + NoItinerary, MSA128, MSA128>; +class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, + NoItinerary, MSA128, MSA128>; + +class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", int_mips_fcle_w, + NoItinerary, MSA128, MSA128>; +class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", int_mips_fcle_d, + NoItinerary, MSA128, MSA128>; + +class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", int_mips_fclt_w, + NoItinerary, MSA128, MSA128>; +class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", int_mips_fclt_d, + NoItinerary, MSA128, MSA128>; + +class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", int_mips_fcne_w, + NoItinerary, MSA128, MSA128>, + IsCommutable; +class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", int_mips_fcne_d, + NoItinerary, MSA128, MSA128>, + IsCommutable; + +class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", int_mips_fcun_w, + NoItinerary, MSA128, MSA128>, + IsCommutable; +class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", int_mips_fcun_d, + NoItinerary, MSA128, MSA128>, + IsCommutable; + +class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", int_mips_fdiv_w, + NoItinerary, MSA128, MSA128>; +class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", int_mips_fdiv_d, + NoItinerary, MSA128, MSA128>; + +class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, + NoItinerary, MSA128, MSA128>; +class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, + NoItinerary, MSA128, MSA128>; + +class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", int_mips_fexp2_w, + NoItinerary, MSA128, MSA128>; +class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", int_mips_fexp2_d, + NoItinerary, MSA128, MSA128>; + +class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, + NoItinerary, MSA128, MSA128>; +class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, + NoItinerary, MSA128, MSA128>; + +class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, + NoItinerary, MSA128, MSA128>; +class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, + NoItinerary, MSA128, MSA128>; + +class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", int_mips_ffint_s_w, + NoItinerary, MSA128, MSA128>; +class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", int_mips_ffint_s_d, + NoItinerary, MSA128, MSA128>; + +class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", int_mips_ffint_u_w, + NoItinerary, MSA128, MSA128>; +class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", int_mips_ffint_u_d, + NoItinerary, MSA128, MSA128>; + +class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, + NoItinerary, MSA128, MSA128>; +class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, + NoItinerary, MSA128, MSA128>; + +class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, + NoItinerary, MSA128, MSA128>; +class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, + NoItinerary, MSA128, MSA128>; + +class FILL_B_DESC : MSA_2R_DESC_BASE<"fill.b", int_mips_fill_b, + NoItinerary, MSA128, GPR32>; +class FILL_H_DESC : MSA_2R_DESC_BASE<"fill.h", int_mips_fill_h, + NoItinerary, MSA128, GPR32>; +class FILL_W_DESC : MSA_2R_DESC_BASE<"fill.w", int_mips_fill_w, + NoItinerary, MSA128, GPR32>; + +class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", int_mips_flog2_w, + NoItinerary, MSA128, MSA128>; +class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", int_mips_flog2_d, + NoItinerary, MSA128, MSA128>; + +class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", int_mips_fmadd_w, + NoItinerary, MSA128, MSA128>; +class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", int_mips_fmadd_d, + NoItinerary, MSA128, MSA128>; + +class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, + NoItinerary, MSA128, MSA128>; +class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, + NoItinerary, MSA128, MSA128>; + +class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, + NoItinerary, MSA128, MSA128>; +class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, + NoItinerary, MSA128, MSA128>; + +class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, + NoItinerary, MSA128, MSA128>; +class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, + NoItinerary, MSA128, MSA128>; + +class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, + NoItinerary, MSA128, MSA128>; +class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, + NoItinerary, MSA128, MSA128>; + +class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", int_mips_fmsub_w, + NoItinerary, MSA128, MSA128>; +class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", int_mips_fmsub_d, + NoItinerary, MSA128, MSA128>; + +class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", int_mips_fmul_w, + NoItinerary, MSA128, MSA128>; +class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", int_mips_fmul_d, + NoItinerary, MSA128, MSA128>; + +class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", int_mips_frint_w, + NoItinerary, MSA128, MSA128>; +class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", int_mips_frint_d, + NoItinerary, MSA128, MSA128>; + +class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, + NoItinerary, MSA128, MSA128>; +class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, + NoItinerary, MSA128, MSA128>; + +class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, + NoItinerary, MSA128, MSA128>; +class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, + NoItinerary, MSA128, MSA128>; + +class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, + NoItinerary, MSA128, MSA128>; +class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, + NoItinerary, MSA128, MSA128>; + +class FSGE_W_DESC : MSA_3RF_DESC_BASE<"fsge.w", int_mips_fsge_w, + NoItinerary, MSA128, MSA128>; +class FSGE_D_DESC : MSA_3RF_DESC_BASE<"fsge.d", int_mips_fsge_d, + NoItinerary, MSA128, MSA128>; + +class FSGT_W_DESC : MSA_3RF_DESC_BASE<"fsgt.w", int_mips_fsgt_w, + NoItinerary, MSA128, MSA128>; +class FSGT_D_DESC : MSA_3RF_DESC_BASE<"fsgt.d", int_mips_fsgt_d, + NoItinerary, MSA128, MSA128>; + +class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, + NoItinerary, MSA128, MSA128>; +class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, + NoItinerary, MSA128, MSA128>; + +class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, + NoItinerary, MSA128, MSA128>; +class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, + NoItinerary, MSA128, MSA128>; + +class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, + NoItinerary, MSA128, MSA128>; +class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, + NoItinerary, MSA128, MSA128>; + +class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", int_mips_fsqrt_w, + NoItinerary, MSA128, MSA128>; +class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", int_mips_fsqrt_d, + NoItinerary, MSA128, MSA128>; + +class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", int_mips_fsub_w, + NoItinerary, MSA128, MSA128>; +class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", int_mips_fsub_d, + NoItinerary, MSA128, MSA128>; + +class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, + NoItinerary, MSA128, MSA128>; +class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, + NoItinerary, MSA128, MSA128>; + +class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, + NoItinerary, MSA128, MSA128>; +class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, + NoItinerary, MSA128, MSA128>; + +class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, + NoItinerary, MSA128, MSA128>; +class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, + NoItinerary, MSA128, MSA128>; + class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", int_mips_ilvev_b, NoItinerary, MSA128, MSA128>; class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", int_mips_ilvev_h, NoItinerary, @@ -1145,6 +1484,130 @@ def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC, Requires<[HasMSA]>; def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC, Requires<[HasMSA]>; def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC, Requires<[HasMSA]>; +def FADD_W : FADD_W_ENC, FADD_W_DESC, Requires<[HasMSA]>; +def FADD_D : FADD_D_ENC, FADD_D_DESC, Requires<[HasMSA]>; + +def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC, Requires<[HasMSA]>; +def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC, Requires<[HasMSA]>; + +def FCLE_W : FCLE_W_ENC, FCLE_W_DESC, Requires<[HasMSA]>; +def FCLE_D : FCLE_D_ENC, FCLE_D_DESC, Requires<[HasMSA]>; + +def FCLT_W : FCLT_W_ENC, FCLT_W_DESC, Requires<[HasMSA]>; +def FCLT_D : FCLT_D_ENC, FCLT_D_DESC, Requires<[HasMSA]>; + +def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC, Requires<[HasMSA]>; +def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC, Requires<[HasMSA]>; + +def FCGE_W : FCGE_W_ENC, FCGE_W_DESC, Requires<[HasMSA]>; +def FCGE_D : FCGE_D_ENC, FCGE_D_DESC, Requires<[HasMSA]>; + +def FCGT_W : FCGT_W_ENC, FCGT_W_DESC, Requires<[HasMSA]>; +def FCGT_D : FCGT_D_ENC, FCGT_D_DESC, Requires<[HasMSA]>; + +def FCNE_W : FCNE_W_ENC, FCNE_W_DESC, Requires<[HasMSA]>; +def FCNE_D : FCNE_D_ENC, FCNE_D_DESC, Requires<[HasMSA]>; + +def FCUN_W : FCUN_W_ENC, FCUN_W_DESC, Requires<[HasMSA]>; +def FCUN_D : FCUN_D_ENC, FCUN_D_DESC, Requires<[HasMSA]>; + +def FDIV_W : FDIV_W_ENC, FDIV_W_DESC, Requires<[HasMSA]>; +def FDIV_D : FDIV_D_ENC, FDIV_D_DESC, Requires<[HasMSA]>; + +def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC, Requires<[HasMSA]>; +def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC, Requires<[HasMSA]>; + +def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC, Requires<[HasMSA]>; +def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC, Requires<[HasMSA]>; + +def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC, Requires<[HasMSA]>; +def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC, Requires<[HasMSA]>; + +def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC, Requires<[HasMSA]>; +def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC, Requires<[HasMSA]>; + +def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC, Requires<[HasMSA]>; +def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC, Requires<[HasMSA]>; + +def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC, Requires<[HasMSA]>; +def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC, Requires<[HasMSA]>; + +def FFQL_W : FFQL_W_ENC, FFQL_W_DESC, Requires<[HasMSA]>; +def FFQL_D : FFQL_D_ENC, FFQL_D_DESC, Requires<[HasMSA]>; + +def FFQR_W : FFQR_W_ENC, FFQR_W_DESC, Requires<[HasMSA]>; +def FFQR_D : FFQR_D_ENC, FFQR_D_DESC, Requires<[HasMSA]>; + +def FILL_B : FILL_B_ENC, FILL_B_DESC, Requires<[HasMSA]>; +def FILL_H : FILL_H_ENC, FILL_H_DESC, Requires<[HasMSA]>; +def FILL_W : FILL_W_ENC, FILL_W_DESC, Requires<[HasMSA]>; + +def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC, Requires<[HasMSA]>; +def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC, Requires<[HasMSA]>; + +def FMADD_W : FMADD_W_ENC, FMADD_W_DESC, Requires<[HasMSA]>; +def FMADD_D : FMADD_D_ENC, FMADD_D_DESC, Requires<[HasMSA]>; + +def FMAX_W : FMAX_W_ENC, FMAX_W_DESC, Requires<[HasMSA]>; +def FMAX_D : FMAX_D_ENC, FMAX_D_DESC, Requires<[HasMSA]>; + +def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC, Requires<[HasMSA]>; +def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC, Requires<[HasMSA]>; + +def FMIN_W : FMIN_W_ENC, FMIN_W_DESC, Requires<[HasMSA]>; +def FMIN_D : FMIN_D_ENC, FMIN_D_DESC, Requires<[HasMSA]>; + +def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC, Requires<[HasMSA]>; +def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC, Requires<[HasMSA]>; + +def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC, Requires<[HasMSA]>; +def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC, Requires<[HasMSA]>; + +def FMUL_W : FMUL_W_ENC, FMUL_W_DESC, Requires<[HasMSA]>; +def FMUL_D : FMUL_D_ENC, FMUL_D_DESC, Requires<[HasMSA]>; + +def FRINT_W : FRINT_W_ENC, FRINT_W_DESC, Requires<[HasMSA]>; +def FRINT_D : FRINT_D_ENC, FRINT_D_DESC, Requires<[HasMSA]>; + +def FRCP_W : FRCP_W_ENC, FRCP_W_DESC, Requires<[HasMSA]>; +def FRCP_D : FRCP_D_ENC, FRCP_D_DESC, Requires<[HasMSA]>; + +def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC, Requires<[HasMSA]>; +def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC, Requires<[HasMSA]>; + +def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC, Requires<[HasMSA]>; +def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC, Requires<[HasMSA]>; + +def FSLE_W : FSLE_W_ENC, FSLE_W_DESC, Requires<[HasMSA]>; +def FSLE_D : FSLE_D_ENC, FSLE_D_DESC, Requires<[HasMSA]>; + +def FSLT_W : FSLT_W_ENC, FSLT_W_DESC, Requires<[HasMSA]>; +def FSLT_D : FSLT_D_ENC, FSLT_D_DESC, Requires<[HasMSA]>; + +def FSGE_W : FSGE_W_ENC, FSGE_W_DESC, Requires<[HasMSA]>; +def FSGE_D : FSGE_D_ENC, FSGE_D_DESC, Requires<[HasMSA]>; + +def FSGT_W : FSGT_W_ENC, FSGT_W_DESC, Requires<[HasMSA]>; +def FSGT_D : FSGT_D_ENC, FSGT_D_DESC, Requires<[HasMSA]>; + +def FSNE_W : FSNE_W_ENC, FSNE_W_DESC, Requires<[HasMSA]>; +def FSNE_D : FSNE_D_ENC, FSNE_D_DESC, Requires<[HasMSA]>; + +def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC, Requires<[HasMSA]>; +def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC, Requires<[HasMSA]>; + +def FSUB_W : FSUB_W_ENC, FSUB_W_DESC, Requires<[HasMSA]>; +def FSUB_D : FSUB_D_ENC, FSUB_D_DESC, Requires<[HasMSA]>; + +def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC, Requires<[HasMSA]>; +def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC, Requires<[HasMSA]>; + +def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC, Requires<[HasMSA]>; +def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC, Requires<[HasMSA]>; + +def FTQ_H : FTQ_H_ENC, FTQ_H_DESC, Requires<[HasMSA]>; +def FTQ_W : FTQ_W_ENC, FTQ_W_DESC, Requires<[HasMSA]>; + def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC, Requires<[HasMSA]>; def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC, Requires<[HasMSA]>; def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC, Requires<[HasMSA]>; @@ -1187,11 +1650,15 @@ def ST_D: ST_D_ENC, ST_D_DESC, Requires<[HasMSA]>; class MSAPat : Pat, Requires<[pred]>; +def LD_FH : MSAPat<(v8f16 (load addr:$addr)), + (LD_H addr:$addr)>; def LD_FW : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>; def LD_FD : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>; +def ST_FH : MSAPat<(store (v8f16 MSA128:$ws), addr:$addr), + (ST_H MSA128:$ws, addr:$addr)>; def ST_FW : MSAPat<(store (v4f32 MSA128:$ws), addr:$addr), (ST_W MSA128:$ws, addr:$addr)>; def ST_FD : MSAPat<(store (v2f64 MSA128:$ws), addr:$addr), diff --git a/test/CodeGen/Mips/msa/2rf.ll b/test/CodeGen/Mips/msa/2rf.ll new file mode 100644 index 00000000000..6283cdf7294 --- /dev/null +++ b/test/CodeGen/Mips/msa/2rf.ll @@ -0,0 +1,192 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_flog2_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_flog2_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_flog2_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_flog2_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.flog2.w(<4 x float> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_flog2_w_RES + ret void +} + +declare <4 x float> @llvm.mips.flog2.w(<4 x float>) nounwind + +; CHECK: llvm_mips_flog2_w_test: +; CHECK: ld.w +; CHECK: flog2.w +; CHECK: st.w +; CHECK: .size llvm_mips_flog2_w_test +; +@llvm_mips_flog2_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_flog2_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_flog2_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_flog2_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.flog2.d(<2 x double> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_flog2_d_RES + ret void +} + +declare <2 x double> @llvm.mips.flog2.d(<2 x double>) nounwind + +; CHECK: llvm_mips_flog2_d_test: +; CHECK: ld.d +; CHECK: flog2.d +; CHECK: st.d +; CHECK: .size llvm_mips_flog2_d_test +; +@llvm_mips_frint_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_frint_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_frint_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_frint_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.frint.w(<4 x float> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_frint_w_RES + ret void +} + +declare <4 x float> @llvm.mips.frint.w(<4 x float>) nounwind + +; CHECK: llvm_mips_frint_w_test: +; CHECK: ld.w +; CHECK: frint.w +; CHECK: st.w +; CHECK: .size llvm_mips_frint_w_test +; +@llvm_mips_frint_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_frint_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_frint_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_frint_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.frint.d(<2 x double> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_frint_d_RES + ret void +} + +declare <2 x double> @llvm.mips.frint.d(<2 x double>) nounwind + +; CHECK: llvm_mips_frint_d_test: +; CHECK: ld.d +; CHECK: frint.d +; CHECK: st.d +; CHECK: .size llvm_mips_frint_d_test +; +@llvm_mips_frcp_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_frcp_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_frcp_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_frcp_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.frcp.w(<4 x float> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_frcp_w_RES + ret void +} + +declare <4 x float> @llvm.mips.frcp.w(<4 x float>) nounwind + +; CHECK: llvm_mips_frcp_w_test: +; CHECK: ld.w +; CHECK: frcp.w +; CHECK: st.w +; CHECK: .size llvm_mips_frcp_w_test +; +@llvm_mips_frcp_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_frcp_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_frcp_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_frcp_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.frcp.d(<2 x double> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_frcp_d_RES + ret void +} + +declare <2 x double> @llvm.mips.frcp.d(<2 x double>) nounwind + +; CHECK: llvm_mips_frcp_d_test: +; CHECK: ld.d +; CHECK: frcp.d +; CHECK: st.d +; CHECK: .size llvm_mips_frcp_d_test +; +@llvm_mips_frsqrt_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_frsqrt_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_frsqrt_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_frsqrt_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.frsqrt.w(<4 x float> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_frsqrt_w_RES + ret void +} + +declare <4 x float> @llvm.mips.frsqrt.w(<4 x float>) nounwind + +; CHECK: llvm_mips_frsqrt_w_test: +; CHECK: ld.w +; CHECK: frsqrt.w +; CHECK: st.w +; CHECK: .size llvm_mips_frsqrt_w_test +; +@llvm_mips_frsqrt_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_frsqrt_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_frsqrt_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_frsqrt_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.frsqrt.d(<2 x double> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_frsqrt_d_RES + ret void +} + +declare <2 x double> @llvm.mips.frsqrt.d(<2 x double>) nounwind + +; CHECK: llvm_mips_frsqrt_d_test: +; CHECK: ld.d +; CHECK: frsqrt.d +; CHECK: st.d +; CHECK: .size llvm_mips_frsqrt_d_test +; +@llvm_mips_fsqrt_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fsqrt_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fsqrt_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fsqrt_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.fsqrt.w(<4 x float> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_fsqrt_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fsqrt.w(<4 x float>) nounwind + +; CHECK: llvm_mips_fsqrt_w_test: +; CHECK: ld.w +; CHECK: fsqrt.w +; CHECK: st.w +; CHECK: .size llvm_mips_fsqrt_w_test +; +@llvm_mips_fsqrt_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fsqrt_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fsqrt_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fsqrt_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.fsqrt.d(<2 x double> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_fsqrt_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fsqrt.d(<2 x double>) nounwind + +; CHECK: llvm_mips_fsqrt_d_test: +; CHECK: ld.d +; CHECK: fsqrt.d +; CHECK: st.d +; CHECK: .size llvm_mips_fsqrt_d_test +; diff --git a/test/CodeGen/Mips/msa/2rf_exup.ll b/test/CodeGen/Mips/msa/2rf_exup.ll new file mode 100644 index 00000000000..54e416de7da --- /dev/null +++ b/test/CodeGen/Mips/msa/2rf_exup.ll @@ -0,0 +1,78 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_fexupl_w_ARG1 = global <8 x half> , align 16 +@llvm_mips_fexupl_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fexupl_w_test() nounwind { +entry: + %0 = load <8 x half>* @llvm_mips_fexupl_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.fexupl.w(<8 x half> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_fexupl_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fexupl.w(<8 x half>) nounwind + +; CHECK: llvm_mips_fexupl_w_test: +; CHECK: ld.h +; CHECK: fexupl.w +; CHECK: st.w +; CHECK: .size llvm_mips_fexupl_w_test +; +@llvm_mips_fexupl_d_ARG1 = global <4 x float> , align 16 +@llvm_mips_fexupl_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fexupl_d_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fexupl_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.fexupl.d(<4 x float> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_fexupl_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fexupl.d(<4 x float>) nounwind + +; CHECK: llvm_mips_fexupl_d_test: +; CHECK: ld.w +; CHECK: fexupl.d +; CHECK: st.d +; CHECK: .size llvm_mips_fexupl_d_test +; +@llvm_mips_fexupr_w_ARG1 = global <8 x half> , align 16 +@llvm_mips_fexupr_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fexupr_w_test() nounwind { +entry: + %0 = load <8 x half>* @llvm_mips_fexupr_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.fexupr.w(<8 x half> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_fexupr_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fexupr.w(<8 x half>) nounwind + +; CHECK: llvm_mips_fexupr_w_test: +; CHECK: ld.h +; CHECK: fexupr.w +; CHECK: st.w +; CHECK: .size llvm_mips_fexupr_w_test +; +@llvm_mips_fexupr_d_ARG1 = global <4 x float> , align 16 +@llvm_mips_fexupr_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fexupr_d_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fexupr_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.fexupr.d(<4 x float> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_fexupr_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fexupr.d(<4 x float>) nounwind + +; CHECK: llvm_mips_fexupr_d_test: +; CHECK: ld.w +; CHECK: fexupr.d +; CHECK: st.d +; CHECK: .size llvm_mips_fexupr_d_test +; diff --git a/test/CodeGen/Mips/msa/2rf_float_int.ll b/test/CodeGen/Mips/msa/2rf_float_int.ll new file mode 100644 index 00000000000..4b2ef22434c --- /dev/null +++ b/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -0,0 +1,78 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> , align 16 +@llvm_mips_ffint_s_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_ffint_s_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_ffint_s_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.ffint.s.w(<4 x i32> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_ffint_s_w_RES + ret void +} + +declare <4 x float> @llvm.mips.ffint.s.w(<4 x i32>) nounwind + +; CHECK: llvm_mips_ffint_s_w_test: +; CHECK: ld.w +; CHECK: ffint_s.w +; CHECK: st.w +; CHECK: .size llvm_mips_ffint_s_w_test +; +@llvm_mips_ffint_s_d_ARG1 = global <2 x i64> , align 16 +@llvm_mips_ffint_s_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_ffint_s_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_ffint_s_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.ffint.s.d(<2 x i64> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_ffint_s_d_RES + ret void +} + +declare <2 x double> @llvm.mips.ffint.s.d(<2 x i64>) nounwind + +; CHECK: llvm_mips_ffint_s_d_test: +; CHECK: ld.d +; CHECK: ffint_s.d +; CHECK: st.d +; CHECK: .size llvm_mips_ffint_s_d_test +; +@llvm_mips_ffint_u_w_ARG1 = global <4 x i32> , align 16 +@llvm_mips_ffint_u_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_ffint_u_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_ffint_u_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.ffint.u.w(<4 x i32> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_ffint_u_w_RES + ret void +} + +declare <4 x float> @llvm.mips.ffint.u.w(<4 x i32>) nounwind + +; CHECK: llvm_mips_ffint_u_w_test: +; CHECK: ld.w +; CHECK: ffint_u.w +; CHECK: st.w +; CHECK: .size llvm_mips_ffint_u_w_test +; +@llvm_mips_ffint_u_d_ARG1 = global <2 x i64> , align 16 +@llvm_mips_ffint_u_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_ffint_u_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_ffint_u_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.ffint.u.d(<2 x i64> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_ffint_u_d_RES + ret void +} + +declare <2 x double> @llvm.mips.ffint.u.d(<2 x i64>) nounwind + +; CHECK: llvm_mips_ffint_u_d_test: +; CHECK: ld.d +; CHECK: ffint_u.d +; CHECK: st.d +; CHECK: .size llvm_mips_ffint_u_d_test +; diff --git a/test/CodeGen/Mips/msa/2rf_fq.ll b/test/CodeGen/Mips/msa/2rf_fq.ll new file mode 100644 index 00000000000..e0f80c09f18 --- /dev/null +++ b/test/CodeGen/Mips/msa/2rf_fq.ll @@ -0,0 +1,78 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_ffql_w_ARG1 = global <8 x i16> , align 16 +@llvm_mips_ffql_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_ffql_w_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_ffql_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_ffql_w_RES + ret void +} + +declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind + +; CHECK: llvm_mips_ffql_w_test: +; CHECK: ld.h +; CHECK: ffql.w +; CHECK: st.w +; CHECK: .size llvm_mips_ffql_w_test +; +@llvm_mips_ffql_d_ARG1 = global <4 x i32> , align 16 +@llvm_mips_ffql_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_ffql_d_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_ffql_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_ffql_d_RES + ret void +} + +declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind + +; CHECK: llvm_mips_ffql_d_test: +; CHECK: ld.w +; CHECK: ffql.d +; CHECK: st.d +; CHECK: .size llvm_mips_ffql_d_test +; +@llvm_mips_ffqr_w_ARG1 = global <8 x i16> , align 16 +@llvm_mips_ffqr_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_ffqr_w_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_ffqr_w_ARG1 + %1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0) + store <4 x float> %1, <4 x float>* @llvm_mips_ffqr_w_RES + ret void +} + +declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind + +; CHECK: llvm_mips_ffqr_w_test: +; CHECK: ld.h +; CHECK: ffqr.w +; CHECK: st.w +; CHECK: .size llvm_mips_ffqr_w_test +; +@llvm_mips_ffqr_d_ARG1 = global <4 x i32> , align 16 +@llvm_mips_ffqr_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_ffqr_d_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_ffqr_d_ARG1 + %1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0) + store <2 x double> %1, <2 x double>* @llvm_mips_ffqr_d_RES + ret void +} + +declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind + +; CHECK: llvm_mips_ffqr_d_test: +; CHECK: ld.w +; CHECK: ffqr.d +; CHECK: st.d +; CHECK: .size llvm_mips_ffqr_d_test +; diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll new file mode 100644 index 00000000000..ef5c0c3db12 --- /dev/null +++ b/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -0,0 +1,116 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_fclass_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fclass_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fclass_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fclass_w_ARG1 + %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0) + store <4 x i32> %1, <4 x i32>* @llvm_mips_fclass_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind + +; CHECK: llvm_mips_fclass_w_test: +; CHECK: ld.w +; CHECK: fclass.w +; CHECK: st.w +; CHECK: .size llvm_mips_fclass_w_test +; +@llvm_mips_fclass_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fclass_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fclass_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fclass_d_ARG1 + %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0) + store <2 x i64> %1, <2 x i64>* @llvm_mips_fclass_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind + +; CHECK: llvm_mips_fclass_d_test: +; CHECK: ld.d +; CHECK: fclass.d +; CHECK: st.d +; CHECK: .size llvm_mips_fclass_d_test +; +@llvm_mips_ftint_s_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_ftint_s_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_ftint_s_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_ftint_s_w_ARG1 + %1 = tail call <4 x i32> @llvm.mips.ftint.s.w(<4 x float> %0) + store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_s_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.ftint.s.w(<4 x float>) nounwind + +; CHECK: llvm_mips_ftint_s_w_test: +; CHECK: ld.w +; CHECK: ftint_s.w +; CHECK: st.w +; CHECK: .size llvm_mips_ftint_s_w_test +; +@llvm_mips_ftint_s_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_ftint_s_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_ftint_s_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_ftint_s_d_ARG1 + %1 = tail call <2 x i64> @llvm.mips.ftint.s.d(<2 x double> %0) + store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_s_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.ftint.s.d(<2 x double>) nounwind + +; CHECK: llvm_mips_ftint_s_d_test: +; CHECK: ld.d +; CHECK: ftint_s.d +; CHECK: st.d +; CHECK: .size llvm_mips_ftint_s_d_test +; +@llvm_mips_ftint_u_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_ftint_u_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_ftint_u_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_ftint_u_w_ARG1 + %1 = tail call <4 x i32> @llvm.mips.ftint.u.w(<4 x float> %0) + store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_u_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.ftint.u.w(<4 x float>) nounwind + +; CHECK: llvm_mips_ftint_u_w_test: +; CHECK: ld.w +; CHECK: ftint_u.w +; CHECK: st.w +; CHECK: .size llvm_mips_ftint_u_w_test +; +@llvm_mips_ftint_u_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_ftint_u_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_ftint_u_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_ftint_u_d_ARG1 + %1 = tail call <2 x i64> @llvm.mips.ftint.u.d(<2 x double> %0) + store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_u_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.ftint.u.d(<2 x double>) nounwind + +; CHECK: llvm_mips_ftint_u_d_test: +; CHECK: ld.d +; CHECK: ftint_u.d +; CHECK: st.d +; CHECK: .size llvm_mips_ftint_u_d_test +; diff --git a/test/CodeGen/Mips/msa/2rf_tq.ll b/test/CodeGen/Mips/msa/2rf_tq.ll new file mode 100644 index 00000000000..190f93ce6ec --- /dev/null +++ b/test/CodeGen/Mips/msa/2rf_tq.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_ftq_h_ARG1 = global <4 x float> , align 16 +@llvm_mips_ftq_h_ARG2 = global <4 x float> , align 16 +@llvm_mips_ftq_h_RES = global <8 x i16> , align 16 + +define void @llvm_mips_ftq_h_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_ftq_h_ARG1 + %1 = load <4 x float>* @llvm_mips_ftq_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.ftq.h(<4 x float> %0, <4 x float> %1) + store <8 x i16> %2, <8 x i16>* @llvm_mips_ftq_h_RES + ret void +} + +declare <8 x i16> @llvm.mips.ftq.h(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_ftq_h_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: ftq.h +; CHECK: st.h +; CHECK: .size llvm_mips_ftq_h_test +; +@llvm_mips_ftq_w_ARG1 = global <2 x double> , align 16 +@llvm_mips_ftq_w_ARG2 = global <2 x double> , align 16 +@llvm_mips_ftq_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_ftq_w_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_ftq_w_ARG1 + %1 = load <2 x double>* @llvm_mips_ftq_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.ftq.w(<2 x double> %0, <2 x double> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_ftq_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.ftq.w(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_ftq_w_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: ftq.w +; CHECK: st.w +; CHECK: .size llvm_mips_ftq_w_test +; diff --git a/test/CodeGen/Mips/msa/3rf.ll b/test/CodeGen/Mips/msa/3rf.ll new file mode 100644 index 00000000000..e2d5a208c08 --- /dev/null +++ b/test/CodeGen/Mips/msa/3rf.ll @@ -0,0 +1,354 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_fadd_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fadd_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fadd_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fadd_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fadd_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fadd.w +; CHECK: st.w +; CHECK: .size llvm_mips_fadd_w_test +; +@llvm_mips_fadd_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fadd_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fadd_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fadd_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fadd_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fadd.d +; CHECK: st.d +; CHECK: .size llvm_mips_fadd_d_test +; +@llvm_mips_fdiv_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fdiv_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fdiv_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fdiv_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fdiv_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fdiv.w +; CHECK: st.w +; CHECK: .size llvm_mips_fdiv_w_test +; +@llvm_mips_fdiv_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fdiv_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fdiv_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fdiv_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fdiv_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fdiv.d +; CHECK: st.d +; CHECK: .size llvm_mips_fdiv_d_test +; +@llvm_mips_fmin_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fmin_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fmin_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fmin_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fmin_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fmin_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fmin_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fmin_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fmin.w +; CHECK: st.w +; CHECK: .size llvm_mips_fmin_w_test +; +@llvm_mips_fmin_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fmin_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fmin_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fmin_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fmin_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fmin_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fmin_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fmin_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fmin.d +; CHECK: st.d +; CHECK: .size llvm_mips_fmin_d_test +; +@llvm_mips_fmin_a_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fmin_a_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fmin_a_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fmin_a_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fmin_a_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fmin_a_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fmin.a.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fmin_a_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fmin.a.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fmin_a_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fmin_a.w +; CHECK: st.w +; CHECK: .size llvm_mips_fmin_a_w_test +; +@llvm_mips_fmin_a_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fmin_a_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fmin_a_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fmin_a_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fmin_a_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fmin_a_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fmin.a.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fmin_a_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fmin.a.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fmin_a_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fmin_a.d +; CHECK: st.d +; CHECK: .size llvm_mips_fmin_a_d_test +; +@llvm_mips_fmax_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fmax_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fmax_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fmax_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fmax_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fmax_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fmax_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fmax_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fmax.w +; CHECK: st.w +; CHECK: .size llvm_mips_fmax_w_test +; +@llvm_mips_fmax_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fmax_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fmax_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fmax_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fmax_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fmax_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fmax_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fmax_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fmax.d +; CHECK: st.d +; CHECK: .size llvm_mips_fmax_d_test +; +@llvm_mips_fmax_a_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fmax_a_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fmax_a_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fmax_a_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fmax_a_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fmax_a_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fmax.a.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fmax_a_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fmax_a_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fmax_a.w +; CHECK: st.w +; CHECK: .size llvm_mips_fmax_a_w_test +; +@llvm_mips_fmax_a_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fmax_a_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fmax_a_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fmax_a_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fmax_a_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fmax_a_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fmax.a.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fmax_a_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fmax_a_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fmax_a.d +; CHECK: st.d +; CHECK: .size llvm_mips_fmax_a_d_test +; +@llvm_mips_fmul_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fmul_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fmul_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fmul_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fmul_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fmul.w +; CHECK: st.w +; CHECK: .size llvm_mips_fmul_w_test +; +@llvm_mips_fmul_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fmul_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fmul_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fmul_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fmul_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fmul.d +; CHECK: st.d +; CHECK: .size llvm_mips_fmul_d_test +; +@llvm_mips_fsub_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fsub_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fsub_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fsub_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fsub_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fsub.w +; CHECK: st.w +; CHECK: .size llvm_mips_fsub_w_test +; +@llvm_mips_fsub_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fsub_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fsub_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fsub_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fsub_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fsub.d +; CHECK: st.d +; CHECK: .size llvm_mips_fsub_d_test +; diff --git a/test/CodeGen/Mips/msa/3rf_4rf.ll b/test/CodeGen/Mips/msa/3rf_4rf.ll new file mode 100644 index 00000000000..cef38fd6e9a --- /dev/null +++ b/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -0,0 +1,102 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_fmadd_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fmadd_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fmadd_w_ARG3 = global <4 x float> , align 16 +@llvm_mips_fmadd_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fmadd_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fmadd_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fmadd_w_ARG2 + %2 = load <4 x float>* @llvm_mips_fmadd_w_ARG3 + %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2) + store <4 x float> %3, <4 x float>* @llvm_mips_fmadd_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fmadd_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fmadd.w +; CHECK: st.w +; CHECK: .size llvm_mips_fmadd_w_test +; +@llvm_mips_fmadd_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fmadd_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fmadd_d_ARG3 = global <2 x double> , align 16 +@llvm_mips_fmadd_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fmadd_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fmadd_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fmadd_d_ARG2 + %2 = load <2 x double>* @llvm_mips_fmadd_d_ARG3 + %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2) + store <2 x double> %3, <2 x double>* @llvm_mips_fmadd_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fmadd_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fmadd.d +; CHECK: st.d +; CHECK: .size llvm_mips_fmadd_d_test +; +@llvm_mips_fmsub_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fmsub_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fmsub_w_ARG3 = global <4 x float> , align 16 +@llvm_mips_fmsub_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fmsub_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fmsub_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fmsub_w_ARG2 + %2 = load <4 x float>* @llvm_mips_fmsub_w_ARG3 + %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2) + store <4 x float> %3, <4 x float>* @llvm_mips_fmsub_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fmsub_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fmsub.w +; CHECK: st.w +; CHECK: .size llvm_mips_fmsub_w_test +; +@llvm_mips_fmsub_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fmsub_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fmsub_d_ARG3 = global <2 x double> , align 16 +@llvm_mips_fmsub_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fmsub_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fmsub_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fmsub_d_ARG2 + %2 = load <2 x double>* @llvm_mips_fmsub_d_ARG3 + %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2) + store <2 x double> %3, <2 x double>* @llvm_mips_fmsub_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fmsub.d(<2 x double>, <2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fmsub_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fmsub.d +; CHECK: st.d +; CHECK: .size llvm_mips_fmsub_d_test +; diff --git a/test/CodeGen/Mips/msa/3rf_exdo.ll b/test/CodeGen/Mips/msa/3rf_exdo.ll new file mode 100644 index 00000000000..45a80116e00 --- /dev/null +++ b/test/CodeGen/Mips/msa/3rf_exdo.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_fexdo_h_ARG1 = global <4 x float> , align 16 +@llvm_mips_fexdo_h_ARG2 = global <4 x float> , align 16 +@llvm_mips_fexdo_h_RES = global <8 x half> , align 16 + +define void @llvm_mips_fexdo_h_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fexdo_h_ARG1 + %1 = load <4 x float>* @llvm_mips_fexdo_h_ARG2 + %2 = tail call <8 x half> @llvm.mips.fexdo.h(<4 x float> %0, <4 x float> %1) + store <8 x half> %2, <8 x half>* @llvm_mips_fexdo_h_RES + ret void +} + +declare <8 x half> @llvm.mips.fexdo.h(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fexdo_h_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fexdo.h +; CHECK: st.h +; CHECK: .size llvm_mips_fexdo_h_test +; +@llvm_mips_fexdo_w_ARG1 = global <2 x double> , align 16 +@llvm_mips_fexdo_w_ARG2 = global <2 x double> , align 16 +@llvm_mips_fexdo_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fexdo_w_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fexdo_w_ARG1 + %1 = load <2 x double>* @llvm_mips_fexdo_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fexdo.w(<2 x double> %0, <2 x double> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fexdo_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fexdo.w(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fexdo_w_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fexdo.w +; CHECK: st.w +; CHECK: .size llvm_mips_fexdo_w_test +; diff --git a/test/CodeGen/Mips/msa/3rf_float_int.ll b/test/CodeGen/Mips/msa/3rf_float_int.ll new file mode 100644 index 00000000000..6b9998d4b12 --- /dev/null +++ b/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_fexp2_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fexp2_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_fexp2_w_RES = global <4 x float> , align 16 + +define void @llvm_mips_fexp2_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fexp2_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_fexp2_w_ARG2 + %2 = tail call <4 x float> @llvm.mips.fexp2.w(<4 x float> %0, <4 x i32> %1) + store <4 x float> %2, <4 x float>* @llvm_mips_fexp2_w_RES + ret void +} + +declare <4 x float> @llvm.mips.fexp2.w(<4 x float>, <4 x i32>) nounwind + +; CHECK: llvm_mips_fexp2_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fexp2.w +; CHECK: st.w +; CHECK: .size llvm_mips_fexp2_w_test +; +@llvm_mips_fexp2_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fexp2_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_fexp2_d_RES = global <2 x double> , align 16 + +define void @llvm_mips_fexp2_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fexp2_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_fexp2_d_ARG2 + %2 = tail call <2 x double> @llvm.mips.fexp2.d(<2 x double> %0, <2 x i64> %1) + store <2 x double> %2, <2 x double>* @llvm_mips_fexp2_d_RES + ret void +} + +declare <2 x double> @llvm.mips.fexp2.d(<2 x double>, <2 x i64>) nounwind + +; CHECK: llvm_mips_fexp2_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fexp2.d +; CHECK: st.d +; CHECK: .size llvm_mips_fexp2_d_test +; diff --git a/test/CodeGen/Mips/msa/3rf_int_float.ll b/test/CodeGen/Mips/msa/3rf_int_float.ll new file mode 100644 index 00000000000..70f73f5777e --- /dev/null +++ b/test/CodeGen/Mips/msa/3rf_int_float.ll @@ -0,0 +1,574 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_fceq_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fceq_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fceq_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fceq_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fceq_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fceq_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fceq.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fceq_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fceq.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fceq_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fceq.w +; CHECK: st.w +; CHECK: .size llvm_mips_fceq_w_test +; +@llvm_mips_fceq_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fceq_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fceq_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fceq_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fceq_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fceq_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fceq.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fceq_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fceq_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fceq.d +; CHECK: st.d +; CHECK: .size llvm_mips_fceq_d_test +; +@llvm_mips_fcge_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fcge_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fcge_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fcge_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fcge_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fcge_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fcge.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fcge_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fcge.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fcge_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fcge.w +; CHECK: st.w +; CHECK: .size llvm_mips_fcge_w_test +; +@llvm_mips_fcge_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fcge_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fcge_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fcge_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fcge_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fcge_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fcge.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fcge_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fcge.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fcge_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fcge.d +; CHECK: st.d +; CHECK: .size llvm_mips_fcge_d_test +; +@llvm_mips_fcgt_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fcgt_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fcgt_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fcgt_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fcgt_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fcgt_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fcgt.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fcgt_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fcgt.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fcgt_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fcgt.w +; CHECK: st.w +; CHECK: .size llvm_mips_fcgt_w_test +; +@llvm_mips_fcgt_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fcgt_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fcgt_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fcgt_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fcgt_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fcgt_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fcgt.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fcgt_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fcgt.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fcgt_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fcgt.d +; CHECK: st.d +; CHECK: .size llvm_mips_fcgt_d_test +; +@llvm_mips_fcle_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fcle_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fcle_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fcle_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fcle_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fcle_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fcle.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fcle_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fcle.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fcle_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fcle.w +; CHECK: st.w +; CHECK: .size llvm_mips_fcle_w_test +; +@llvm_mips_fcle_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fcle_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fcle_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fcle_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fcle_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fcle_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fcle.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fcle_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fcle.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fcle_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fcle.d +; CHECK: st.d +; CHECK: .size llvm_mips_fcle_d_test +; +@llvm_mips_fclt_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fclt_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fclt_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fclt_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fclt_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fclt_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fclt.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fclt_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fclt.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fclt_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fclt.w +; CHECK: st.w +; CHECK: .size llvm_mips_fclt_w_test +; +@llvm_mips_fclt_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fclt_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fclt_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fclt_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fclt_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fclt_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fclt.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fclt_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fclt.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fclt_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fclt.d +; CHECK: st.d +; CHECK: .size llvm_mips_fclt_d_test +; +@llvm_mips_fcne_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fcne_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fcne_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fcne_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fcne_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fcne_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fcne.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fcne_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fcne.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fcne_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fcne.w +; CHECK: st.w +; CHECK: .size llvm_mips_fcne_w_test +; +@llvm_mips_fcne_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fcne_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fcne_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fcne_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fcne_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fcne_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fcne.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fcne_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fcne.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fcne_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fcne.d +; CHECK: st.d +; CHECK: .size llvm_mips_fcne_d_test +; +@llvm_mips_fcun_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fcun_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fcun_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fcun_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fcun_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fcun_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fcun.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fcun_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fcun.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fcun_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fcun.w +; CHECK: st.w +; CHECK: .size llvm_mips_fcun_w_test +; +@llvm_mips_fcun_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fcun_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fcun_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fcun_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fcun_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fcun_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fcun.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fcun_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fcun.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fcun_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fcun.d +; CHECK: st.d +; CHECK: .size llvm_mips_fcun_d_test +; +@llvm_mips_fseq_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fseq_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fseq_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fseq_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fseq_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fseq_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fseq.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fseq_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fseq.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fseq_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fseq.w +; CHECK: st.w +; CHECK: .size llvm_mips_fseq_w_test +; +@llvm_mips_fseq_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fseq_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fseq_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fseq_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fseq_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fseq_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fseq.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fseq_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fseq.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fseq_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fseq.d +; CHECK: st.d +; CHECK: .size llvm_mips_fseq_d_test +; +@llvm_mips_fsge_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fsge_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fsge_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fsge_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fsge_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fsge_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fsge.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fsge_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fsge.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fsge_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fsge.w +; CHECK: st.w +; CHECK: .size llvm_mips_fsge_w_test +; +@llvm_mips_fsge_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fsge_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fsge_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fsge_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fsge_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fsge_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fsge.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fsge_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fsge.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fsge_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fsge.d +; CHECK: st.d +; CHECK: .size llvm_mips_fsge_d_test +; +@llvm_mips_fsgt_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fsgt_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fsgt_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fsgt_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fsgt_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fsgt_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fsgt.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fsgt_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fsgt.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fsgt_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fsgt.w +; CHECK: st.w +; CHECK: .size llvm_mips_fsgt_w_test +; +@llvm_mips_fsgt_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fsgt_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fsgt_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fsgt_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fsgt_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fsgt_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fsgt.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fsgt_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fsgt.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fsgt_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fsgt.d +; CHECK: st.d +; CHECK: .size llvm_mips_fsgt_d_test +; +@llvm_mips_fsle_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fsle_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fsle_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fsle_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fsle_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fsle_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fsle.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fsle_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fsle.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fsle_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fsle.w +; CHECK: st.w +; CHECK: .size llvm_mips_fsle_w_test +; +@llvm_mips_fsle_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fsle_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fsle_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fsle_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fsle_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fsle_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fsle.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fsle_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fsle.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fsle_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fsle.d +; CHECK: st.d +; CHECK: .size llvm_mips_fsle_d_test +; +@llvm_mips_fslt_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fslt_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fslt_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fslt_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fslt_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fslt_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fslt.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fslt_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fslt.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fslt_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fslt.w +; CHECK: st.w +; CHECK: .size llvm_mips_fslt_w_test +; +@llvm_mips_fslt_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fslt_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fslt_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fslt_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fslt_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fslt_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fslt.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fslt_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fslt.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fslt_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fslt.d +; CHECK: st.d +; CHECK: .size llvm_mips_fslt_d_test +; +@llvm_mips_fsne_w_ARG1 = global <4 x float> , align 16 +@llvm_mips_fsne_w_ARG2 = global <4 x float> , align 16 +@llvm_mips_fsne_w_RES = global <4 x i32> , align 16 + +define void @llvm_mips_fsne_w_test() nounwind { +entry: + %0 = load <4 x float>* @llvm_mips_fsne_w_ARG1 + %1 = load <4 x float>* @llvm_mips_fsne_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.fsne.w(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_fsne_w_RES + ret void +} + +declare <4 x i32> @llvm.mips.fsne.w(<4 x float>, <4 x float>) nounwind + +; CHECK: llvm_mips_fsne_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: fsne.w +; CHECK: st.w +; CHECK: .size llvm_mips_fsne_w_test +; +@llvm_mips_fsne_d_ARG1 = global <2 x double> , align 16 +@llvm_mips_fsne_d_ARG2 = global <2 x double> , align 16 +@llvm_mips_fsne_d_RES = global <2 x i64> , align 16 + +define void @llvm_mips_fsne_d_test() nounwind { +entry: + %0 = load <2 x double>* @llvm_mips_fsne_d_ARG1 + %1 = load <2 x double>* @llvm_mips_fsne_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.fsne.d(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_fsne_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fsne.d(<2 x double>, <2 x double>) nounwind + +; CHECK: llvm_mips_fsne_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: fsne.d +; CHECK: st.d +; CHECK: .size llvm_mips_fsne_d_test +; -- 2.34.1