From d1c321a89ab999b9bb602b0f398ecd4c2022262c Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Thu, 12 Feb 2009 00:02:55 +0000 Subject: [PATCH] Move debug loc info along when the spiller creates new instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.cpp | 101 ++++++++++++++++++---------- lib/Target/Alpha/AlphaInstrInfo.cpp | 63 +++++++++++------ lib/Target/CellSPU/SPUInstrInfo.cpp | 40 ++++++----- lib/Target/IA64/IA64InstrInfo.cpp | 73 +++++++++++--------- lib/Target/Mips/MipsInstrInfo.cpp | 57 ++++++++++------ lib/Target/PIC16/PIC16InstrInfo.cpp | 15 +++-- lib/Target/PowerPC/PPCInstrInfo.cpp | 83 +++++++++++++---------- lib/Target/PowerPC/PPCInstrInfo.h | 2 +- lib/Target/Sparc/SparcInstrInfo.cpp | 71 ++++++++++++------- lib/Target/XCore/XCoreInstrInfo.cpp | 56 +++++++++------ 10 files changed, 349 insertions(+), 212 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 0c55f938b2f..8578284a35d 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -243,17 +243,20 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, // Can't encode it in a so_imm operand. This transformation will // add more than 1 instruction. Abandon! return NULL; - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(SOImmVal) .addImm(Pred).addReg(0).addReg(0); } else if (Amt != 0) { ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) .addImm(Pred).addReg(0).addReg(0); } else - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -263,11 +266,13 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Amt = ARM_AM::getAM3Offset(OffImm); if (OffReg == 0) // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(Amt) .addImm(Pred).addReg(0).addReg(0); else - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -277,19 +282,23 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, std::vector NewMIs; if (isPre) { if (isLoad) - MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc), MI->getOperand(0).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); NewMIs.push_back(MemMI); NewMIs.push_back(UpdateMI); } else { if (isLoad) - MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc), MI->getOperand(0).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); if (WB.isDead()) UpdateMI->getOperand(0).setIsDead(); @@ -474,19 +483,22 @@ bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB, return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); else - AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg) + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) .addReg(SrcReg))); } else if (DestRC == ARM::SPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) .addReg(SrcReg)); else if (DestRC == ARM::DPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) .addReg(SrcReg)); else return false; @@ -512,33 +524,37 @@ void ARMInstrInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) + BuildMI(MBB, I, DL, get(ARM::tSpill)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0); else - AddDefaultPred(BuildMI(MBB, I, get(ARM::STR)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0)); } } void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const{ unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); @@ -572,28 +588,31 @@ void ARMInstrInfo:: loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tRestore), DestReg) + BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) .addFrameIndex(FI).addImm(0); else - AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) .addFrameIndex(FI).addImm(0)); } } void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { @@ -630,7 +649,10 @@ bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, if (!AFI->isThumbFunction() || CSI.empty()) return false; - MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); for (unsigned i = CSI.size(); i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); // Add the callee-saved register as live-in. It's killed at the spill. @@ -686,12 +708,14 @@ MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(ARM::STR)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::LDR)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) + .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -703,7 +727,8 @@ MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg)) // tSpill cannot take a high register operand. break; - NewMI = BuildMI(MF, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); @@ -711,7 +736,7 @@ MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, // tRestore cannot target a high register operand. break; bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::tRestore)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0); } @@ -722,11 +747,13 @@ MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); - NewMI = BuildMI(MF, get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) + .addReg(SrcReg).addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); - NewMI = BuildMI(MF, get(ARM::FLDS), DstReg).addFrameIndex(FI) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg) + .addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -737,12 +764,14 @@ MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(ARM::FSTD)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) + .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } break; diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 0974699fa0c..3922a246cbf 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -105,8 +105,8 @@ static bool isAlphaIntCondCode(unsigned Opcode) { } unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, - MachineBasicBlock *FBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -138,22 +138,31 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, } bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else if (DestRC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else if (DestRC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else { // Attempt to copy register that is not GPR or FPR return false; @@ -164,22 +173,26 @@ bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, void AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIdx, - const TargetRegisterClass *RC) const { + MachineBasicBlock::iterator MI, + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC) const { //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " // << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STS)) + BuildMI(MBB, MI, DL, get(Alpha::STS)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STT)) + BuildMI(MBB, MI, DL, get(Alpha::STT)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STQ)) + BuildMI(MBB, MI, DL, get(Alpha::STQ)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else @@ -219,14 +232,17 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, const TargetRegisterClass *RC) const { //cerr << "Trying to load " << getPrettyName(DestReg) << " to " // << FrameIdx << "\n"; + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDS), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDT), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDQ), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); @@ -279,7 +295,8 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, bool isKill = MI->getOperand(1).isKill(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) + .addReg(InReg, false, false, isKill) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move @@ -287,7 +304,8 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, bool isDead = MI->getOperand(0).isDead(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) + .addReg(OutReg, true, false, false, isDead) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } @@ -410,7 +428,10 @@ unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31) .addReg(Alpha::R31); } diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index ded83247610..182b3a75170 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -259,22 +259,25 @@ bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, // we instruction select bitconvert i64 -> f64 as a noop for example, so our // types have no specific meaning. + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == SPU::R8CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R16CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R32CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R32FPRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R64CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R64FPRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg); } else if (DestRC == SPU::GPRCRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg); } else if (DestRC == SPU::VECREGRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg); } else { // Attempt to copy unknown/unsupported register class! return false; @@ -312,15 +315,17 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, abort(); } - addFrameReference(BuildMI(MBB, MI, get(opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(opc)) .addReg(SrcReg, false, false, isKill), FrameIdx); } void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const { cerr << "storeRegToAddr() invoked!\n"; abort(); @@ -388,7 +393,9 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, abort(); } - addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(opc)).addReg(DestReg), FrameIdx); } /*! @@ -495,7 +502,8 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); if (FrameIndex < SPUFrameInfo::maxFrameOffset()) { - MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32)); + MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), + get(SPU::STQDr32)); MIB.addReg(InReg, false, false, isKill); NewMI = addFrameReference(MIB, FrameIndex); @@ -503,7 +511,7 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)); MIB.addReg(OutReg, true, false, false, isDead); Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index a3009b2078b..a6e4d97f6e3 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -62,21 +62,24 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, } bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode // (SrcReg) DestReg = cmp.eq.unc(r0, r0) - BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg) + BuildMI(MBB, MI, DL, get(IA64::PCMPEQUNC), DestReg) .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); else // otherwise, MOV works (for both gen. regs and FP regs) - BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(IA64::MOV), DestReg).addReg(SrcReg); return true; } @@ -86,30 +89,34 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::PRRegisterClass) { /* we use IA64::r2 as a temporary register for doing this hackery. */ // first we load 0: - BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0); + BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0); // then conditionally add 1: - BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) + BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) .addImm(1).addReg(SrcReg, false, false, isKill); // and then store it to the stack - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2); + BuildMI(MBB, MI, DL, get(IA64::ST8)) + .addFrameIndex(FrameIdx) + .addReg(IA64::r2); } else assert(0 && "sorry, I don't know how to store this sort of reg in the stack\n"); } void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { @@ -140,28 +147,34 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC)const{ + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC)const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); + BuildMI(MBB, MI, DL, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); - } else if (RC == IA64::PRRegisterClass) { - // first we load a byte from the stack into r2, our 'predicate hackery' - // scratch reg - BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); - // then we compare it to zero. If it _is_ zero, compare-not-equal to - // r0 gives us 0, which is what we want, so that's nice. - BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0); - } else assert(0 && - "sorry, I don't know how to load this sort of reg from the stack\n"); + BuildMI(MBB, MI, DL, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); + } else if (RC == IA64::PRRegisterClass) { + // first we load a byte from the stack into r2, our 'predicate hackery' + // scratch reg + BuildMI(MBB, MI, DL, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); + // then we compare it to zero. If it _is_ zero, compare-not-equal to + // r0 gives us 0, which is what we want, so that's nice. + BuildMI(MBB, MI, DL, get(IA64::CMPNE), DestReg) + .addReg(IA64::r2) + .addReg(IA64::r0); + } else { + assert(0 && + "sorry, I don't know how to load this sort of reg from the stack\n"); + } } void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 758e9bea5ad..167aa45632d 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -118,7 +118,9 @@ isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const void MipsInstrInfo:: insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(Mips::NOP)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + BuildMI(MBB, MI, DL, get(Mips::NOP)); } bool MipsInstrInfo:: @@ -126,22 +128,25 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC != SrcRC) { if ((DestRC == Mips::CPURegsRegisterClass) && (SrcRC == Mips::FGR32RegisterClass)) - BuildMI(MBB, I, get(Mips::MFC1), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg); else if ((DestRC == Mips::CPURegsRegisterClass) && (SrcRC == Mips::AFGR32RegisterClass)) - BuildMI(MBB, I, get(Mips::MFC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MFC1A), DestReg).addReg(SrcReg); else if ((DestRC == Mips::FGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg); else if ((DestRC == Mips::AFGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg); else if ((DestRC == Mips::AFGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg); else if ((SrcRC == Mips::CCRRegisterClass) && (SrcReg == Mips::FCR31)) return true; // This register is used implicitly, no copy needed. @@ -151,11 +156,11 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, else if ((DestRC == Mips::HILORegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) { unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO; - BuildMI(MBB, I, get(Opc), DestReg); + BuildMI(MBB, I, DL, get(Opc), DestReg); } else if ((SrcRC == Mips::HILORegisterClass) && (DestRC == Mips::CPURegsRegisterClass)) { unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO; - BuildMI(MBB, I, get(Opc), DestReg); + BuildMI(MBB, I, DL, get(Opc), DestReg); } else // DestRC != SrcRC, Can't copy this register return false; @@ -164,14 +169,14 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } if (DestRC == Mips::CPURegsRegisterClass) - BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) + BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) .addReg(SrcReg); else if (DestRC == Mips::FGR32RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg); else if (DestRC == Mips::AFGR32RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg); else if (DestRC == Mips::AFGR64RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); else // Can't copy this register return false; @@ -181,10 +186,14 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void MipsInstrInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FI, - const TargetRegisterClass *RC) const + unsigned SrcReg, bool isKill, int FI, + const TargetRegisterClass *RC) const { unsigned Opc; + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == Mips::CPURegsRegisterClass) Opc = Mips::SW; else if (RC == Mips::FGR32RegisterClass) @@ -196,7 +205,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, else assert(0 && "Can't store this register to stack slot"); - BuildMI(MBB, I, get(Opc)).addReg(SrcReg, false, false, isKill) + BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI); } @@ -248,12 +257,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, else assert(0 && "Can't load this register from stack slot"); - BuildMI(MBB, I, get(Opc), DestReg).addImm(0).addFrameIndex(FI); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI); } void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc; if (RC == Mips::CPURegsRegisterClass) @@ -299,12 +310,13 @@ foldMemoryOperandImpl(MachineFunction &MF, if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(2).getReg(); bool isKill = MI->getOperand(2).isKill(); - NewMI = BuildMI(MF, get(Mips::SW)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) + .addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(Mips::LW)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } @@ -331,12 +343,13 @@ foldMemoryOperandImpl(MachineFunction &MF, if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(StoreOpc)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) + .addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI) ; } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(LoadOpc)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp index 47ac6d31703..0066e67209d 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.cpp +++ b/lib/Target/PIC16/PIC16InstrInfo.cpp @@ -69,6 +69,8 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); const Function *Func = MBB.getParent()->getFunction(); const std::string FuncName = Func->getName(); @@ -80,7 +82,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, if (RC == PIC16::GPRRegisterClass) { //MachineFunction &MF = *MBB.getParent(); //MachineRegisterInfo &RI = MF.getRegInfo(); - BuildMI(MBB, I, get(PIC16::movwf)) + BuildMI(MBB, I, DL, get(PIC16::movwf)) .addReg(SrcReg, false, false, isKill) .addImm(FI) .addExternalSymbol(tmpName) @@ -96,6 +98,8 @@ void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); const Function *Func = MBB.getParent()->getFunction(); const std::string FuncName = Func->getName(); @@ -107,7 +111,7 @@ void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, if (RC == PIC16::GPRRegisterClass) { //MachineFunction &MF = *MBB.getParent(); //MachineRegisterInfo &RI = MF.getRegInfo(); - BuildMI(MBB, I, get(PIC16::movf), DestReg) + BuildMI(MBB, I, DL, get(PIC16::movf), DestReg) .addImm(FI) .addExternalSymbol(tmpName) .addImm(1); // Emit banksel for it. @@ -123,13 +127,16 @@ bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == PIC16::FSR16RegisterClass) { - BuildMI(MBB, I, get(PIC16::copy_fsr), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg); return true; } if (DestRC == PIC16::GPRRegisterClass) { - BuildMI(MBB, I, get(PIC16::copy_w), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg); return true; } diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 3e0c7e73ac3..0097393b722 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -174,7 +174,7 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { // Create a new instruction. unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); bool Reg0IsDead = MI->getOperand(0).isDead(); - return BuildMI(MF, MI->getDesc()) + return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) .addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg1, false, false, Reg1IsKill) @@ -197,7 +197,10 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(PPC::NOP)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + BuildMI(MBB, MI, DL, get(PPC::NOP)); } @@ -321,20 +324,23 @@ bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == PPC::GPRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::G8RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::F4RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg); } else if (DestRC == PPC::F8RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg); } else if (DestRC == PPC::CRRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg); } else if (DestRC == PPC::VRRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::CRBITRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); } else { // Attempt to copy register that is not GPR or FPR return false; @@ -515,37 +521,37 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } void -PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, +PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs)const{ if (RC == PPC::GPRCRegisterClass) { if (DestReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg), - FrameIdx)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), + DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11), - FrameIdx)); - NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), + PPC::R11), FrameIdx)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); } } else if (RC == PPC::G8RCRegisterClass) { if (DestReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11), - FrameIdx)); - NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), + PPC::R11), FrameIdx)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0), FrameIdx)); // If the reloaded register isn't CR0, shift the bits right so that they are @@ -553,11 +559,11 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, if (DestReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0)); } else if (RC == PPC::CRBITRCRegisterClass) { unsigned Reg = 0; @@ -578,7 +584,7 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN) Reg = PPC::CR7; - return LoadRegFromStackSlot(MF, Reg, FrameIdx, + return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, PPC::CRRCRegisterClass, NewMIs); } else if (RC == PPC::VRRCRegisterClass) { @@ -587,9 +593,9 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, // Dest = LVX 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) .addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -604,7 +610,9 @@ PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, const TargetRegisterClass *RC) const { MachineFunction &MF = *MBB.getParent(); SmallVector NewMIs; - LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); } @@ -614,7 +622,8 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs)const{ if (Addr[0].isFI()) { - LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs); + LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(), + DestReg, Addr[0].getIndex(), RC, NewMIs); return; } @@ -668,13 +677,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -683,13 +692,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -697,13 +706,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -711,13 +720,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index f1903984639..492634c979e 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -69,7 +69,7 @@ class PPCInstrInfo : public TargetInstrInfoImpl { unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; - void LoadRegFromStackSlot(MachineFunction &MF, + void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index a6cee0e578c..cbfde30ba16 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -114,21 +114,24 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, } bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); + BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); else if (DestRC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg); else if (DestRC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) + BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) .addReg(SrcReg); else // Can't copy this register @@ -141,24 +144,27 @@ void SparcInstrInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + // On the order of operands here: think "[FrameIdx + 0] = SrcReg". if (RC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, false, false, isKill); else if (RC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, false, false, isKill); else if (RC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, false, false, isKill); else assert(0 && "Can't store this register to stack slot"); } void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == SP::IntRegsRegisterClass) @@ -190,19 +196,22 @@ void SparcInstrInfo:: loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); else if (RC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); else if (RC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); else assert(0 && "Can't load this register from stack slot"); } void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == SP::IntRegsRegisterClass) @@ -243,11 +252,15 @@ MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&& MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) { if (OpNum == 0) // COPY -> STORE - NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0) - .addReg(MI->getOperand(2).getReg()); + NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri)) + .addFrameIndex(FI) + .addImm(0) + .addReg(MI->getOperand(2).getReg()); else // COPY -> LOAD - NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg()) - .addFrameIndex(FI).addImm(0); + NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri), + MI->getOperand(0).getReg()) + .addFrameIndex(FI) + .addImm(0); } break; case SP::FMOVS: @@ -257,13 +270,19 @@ MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri)) - .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill); + NewMI = BuildMI(MF, MI->getDebugLoc(), + get(isFloat ? SP::STFri : SP::STDFri)) + .addFrameIndex(FI) + .addImm(0) + .addReg(SrcReg, false, false, isKill); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri)) - .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0); + NewMI = BuildMI(MF, MI->getDebugLoc(), + get(isFloat ? SP::LDFri : SP::LDDFri)) + .addReg(DstReg, true, false, false, isDead) + .addFrameIndex(FI) + .addImm(0); } break; } diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 98b4e5cadfd..4328411024a 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -353,13 +353,18 @@ XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { } bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == SrcRC) { if (DestRC == XCore::GRRegsRegisterClass) { - BuildMI(MBB, I, get(XCore::ADD_2rus), DestReg).addReg(SrcReg).addImm(0); + BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) + .addReg(SrcReg) + .addImm(0); return true; } else { return false; @@ -368,24 +373,31 @@ bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB, if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP && DestRC == XCore::GRRegsRegisterClass) { - BuildMI(MBB, I, get(XCore::LDAWSP_ru6), DestReg).addImm(0); + BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg) + .addImm(0); return true; } if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP && SrcRC == XCore::GRRegsRegisterClass) { - BuildMI(MBB, I, get(XCore::SETSP_1r)).addReg(SrcReg); + BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) + .addReg(SrcReg); return true; } return false; } void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC) const + MachineBasicBlock::iterator I, + unsigned SrcReg, bool isKill, + int FrameIndex, + const TargetRegisterClass *RC) const { - BuildMI(MBB, I, get(XCore::STWFI)).addReg(SrcReg, false, false, isKill) - .addFrameIndex(FrameIndex).addImm(0); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(XCore::STWFI)) + .addReg(SrcReg, false, false, isKill) + .addFrameIndex(FrameIndex) + .addImm(0); } void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -397,12 +409,15 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, int FrameIndex, - const TargetRegisterClass *RC) const + MachineBasicBlock::iterator I, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC) const { - BuildMI(MBB, I, get(XCore::LDWFI), DestReg).addFrameIndex(FrameIndex) - .addImm(0); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) + .addFrameIndex(FrameIndex) + .addImm(0); } void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -426,6 +441,9 @@ bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, XCoreFunctionInfo *XFI = MF->getInfo(); bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); for (std::vector::const_iterator it = CSI.begin(); it != CSI.end(); ++it) { @@ -433,10 +451,10 @@ bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MBB.addLiveIn(it->getReg()); storeRegToStackSlot(MBB, MI, it->getReg(), true, - it->getFrameIdx(), it->getRegClass()); + it->getFrameIdx(), it->getRegClass()); if (emitFrameMoves) { unsigned SaveLabelId = MMI->NextLabelID(); - BuildMI(MBB, MI, get(XCore::DBG_LABEL)).addImm(SaveLabelId); + BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addImm(SaveLabelId); XFI->getSpillLabels().push_back( std::pair(SaveLabelId, *it)); } -- 2.34.1