From d3ab717935803275fc7af3915be0c1678feec001 Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Tue, 24 Mar 2015 09:17:25 +0000 Subject: [PATCH] Use std::bitset for SubtargetFeatures Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233055 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/MC/MCInstPrinter.h | 9 +- include/llvm/MC/MCInstrDesc.h | 4 +- include/llvm/MC/MCSubtargetInfo.h | 16 +- include/llvm/MC/SubtargetFeature.h | 26 ++- lib/MC/MCSubtargetInfo.cpp | 9 +- lib/MC/SubtargetFeature.cpp | 23 +-- lib/Target/AArch64/Utils/AArch64BaseInfo.cpp | 9 +- lib/Target/AArch64/Utils/AArch64BaseInfo.h | 10 +- lib/Target/ARM/ARMAsmPrinter.cpp | 2 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- lib/Target/ARM/ARMSubtarget.cpp | 4 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 156 +++++++++--------- .../ARM/Disassembler/ARMDisassembler.cpp | 71 ++++---- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 14 +- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h | 2 +- .../ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 4 +- .../ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 8 +- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 78 ++++----- .../Mips/Disassembler/MipsDisassembler.cpp | 10 +- .../Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 4 +- .../Mips/MCTargetDesc/MipsTargetStreamer.cpp | 38 ++--- .../PowerPC/Disassembler/PPCDisassembler.cpp | 2 +- .../R600/MCTargetDesc/R600MCCodeEmitter.cpp | 4 +- .../Sparc/InstPrinter/SparcInstPrinter.cpp | 2 +- .../X86/AsmParser/X86AsmInstrumentation.cpp | 10 +- lib/Target/X86/AsmParser/X86AsmParser.cpp | 25 +-- .../X86/Disassembler/X86Disassembler.cpp | 19 +-- .../X86/InstPrinter/X86ATTInstPrinter.cpp | 2 +- .../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 6 +- utils/TableGen/AsmMatcherEmitter.cpp | 12 +- utils/TableGen/FixedLenDecoderEmitter.cpp | 10 +- utils/TableGen/InstrInfoEmitter.cpp | 8 +- utils/TableGen/SubtargetEmitter.cpp | 57 +++---- 33 files changed, 348 insertions(+), 308 deletions(-) diff --git a/include/llvm/MC/MCInstPrinter.h b/include/llvm/MC/MCInstPrinter.h index dce3a0690b3..028d24ed72b 100644 --- a/include/llvm/MC/MCInstPrinter.h +++ b/include/llvm/MC/MCInstPrinter.h @@ -10,6 +10,7 @@ #ifndef LLVM_MC_MCINSTPRINTER_H #define LLVM_MC_MCINSTPRINTER_H +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/Format.h" @@ -41,7 +42,7 @@ protected: const MCRegisterInfo &MRI; /// The current set of available features. - uint64_t AvailableFeatures; + FeatureBitset AvailableFeatures; /// True if we are printing marked up assembly. bool UseMarkup; @@ -58,7 +59,7 @@ public: MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, const MCRegisterInfo &mri) : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri), - AvailableFeatures(0), UseMarkup(0), PrintImmHex(0), + AvailableFeatures(), UseMarkup(0), PrintImmHex(0), PrintHexStyle(HexStyle::C) {} virtual ~MCInstPrinter(); @@ -78,8 +79,8 @@ public: /// printRegName - Print the assembler register name. virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; - uint64_t getAvailableFeatures() const { return AvailableFeatures; } - void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; } + const FeatureBitset& getAvailableFeatures() const { return AvailableFeatures; } + void setAvailableFeatures(const FeatureBitset& Value) { AvailableFeatures = Value; } bool getUseMarkup() const { return UseMarkup; } void setUseMarkup(bool Value) { UseMarkup = Value; } diff --git a/include/llvm/MC/MCInstrDesc.h b/include/llvm/MC/MCInstrDesc.h index 360989305d3..459efadb21f 100644 --- a/include/llvm/MC/MCInstrDesc.h +++ b/include/llvm/MC/MCInstrDesc.h @@ -150,7 +150,7 @@ public: const uint16_t *ImplicitUses; // Registers implicitly read by this instr const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands - uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any + FeatureBitset DeprecatedFeatureMask; // Feature bits that this is deprecated on, if any // A complex method to determine is a certain is deprecated or not, and return // the reason for deprecation. bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &); @@ -173,7 +173,7 @@ public: std::string &Info) const { if (ComplexDeprecationInfo) return ComplexDeprecationInfo(MI, STI, Info); - if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) { + if ((STI.getFeatureBits() & DeprecatedFeatureMask).any()) { // FIXME: it would be nice to include the subtarget feature here. Info = "deprecated"; return true; diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h index 3984a1fb21b..1778a6d13fb 100644 --- a/include/llvm/MC/MCSubtargetInfo.h +++ b/include/llvm/MC/MCSubtargetInfo.h @@ -42,7 +42,7 @@ class MCSubtargetInfo { const InstrStage *Stages; // Instruction itinerary stages const unsigned *OperandCycles; // Itinerary operand cycles const unsigned *ForwardingPaths; // Forwarding paths - uint64_t FeatureBits; // Feature bits for current CPU + FS + FeatureBitset FeatureBits; // Feature bits for current CPU + FS public: void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, @@ -67,13 +67,13 @@ public: /// getFeatureBits - Return the feature bits. /// - uint64_t getFeatureBits() const { + const FeatureBitset& getFeatureBits() const { return FeatureBits; } /// setFeatureBits - Set the feature bits. /// - void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; } + void setFeatureBits(FeatureBitset& FeatureBits_) { FeatureBits = FeatureBits_; } /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with /// feature string). Recompute feature bits and scheduling model. @@ -84,11 +84,15 @@ public: /// ToggleFeature - Toggle a feature and returns the re-computed feature /// bits. This version does not change the implied bits. - uint64_t ToggleFeature(uint64_t FB); + FeatureBitset ToggleFeature(uint64_t FB); /// ToggleFeature - Toggle a feature and returns the re-computed feature - /// bits. This version will also change all implied bits. - uint64_t ToggleFeature(StringRef FS); + /// bits. This version does not change the implied bits. + FeatureBitset ToggleFeature(const FeatureBitset& FB); + + /// ToggleFeature - Toggle a set of features and returns the re-computed + /// feature bits. This version will also change all implied bits. + FeatureBitset ToggleFeature(StringRef FS); /// getSchedModelForCPU - Get the machine model of a CPU. /// diff --git a/include/llvm/MC/SubtargetFeature.h b/include/llvm/MC/SubtargetFeature.h index bfecb8ba6ab..fd096382686 100644 --- a/include/llvm/MC/SubtargetFeature.h +++ b/include/llvm/MC/SubtargetFeature.h @@ -21,11 +21,29 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/Triple.h" #include "llvm/Support/DataTypes.h" +#include namespace llvm { class raw_ostream; class StringRef; +// A container class for subtarget features. +// This is convenient because std::bitset does not have a constructor +// with an initializer list of set bits. +const unsigned MAX_SUBTARGET_FEATURES = 64; +class FeatureBitset : public std::bitset { +public: + // Cannot inherit constructors because it's not supported by VC++.. + FeatureBitset() : bitset() {} + + FeatureBitset(const bitset& B) : bitset(B) {} + + FeatureBitset(std::initializer_list Init) : bitset() { + for (auto I = Init.begin() , E = Init.end(); I != E; ++I) + set(*I); + } +}; + //===----------------------------------------------------------------------===// /// /// SubtargetFeatureKV - Used to provide key value pairs for feature and @@ -34,8 +52,8 @@ namespace llvm { struct SubtargetFeatureKV { const char *Key; // K-V key string const char *Desc; // Help descriptor - uint64_t Value; // K-V integer value - uint64_t Implies; // K-V bit mask + FeatureBitset Value; // K-V integer value + FeatureBitset Implies; // K-V bit mask // Compare routine for std::lower_bound bool operator<(StringRef S) const { @@ -82,11 +100,11 @@ public: /// ToggleFeature - Toggle a feature and returns the newly updated feature /// bits. - uint64_t ToggleFeature(uint64_t Bits, StringRef String, + FeatureBitset ToggleFeature(FeatureBitset Bits, StringRef String, ArrayRef FeatureTable); /// Get feature bits of a CPU. - uint64_t getFeatureBits(StringRef CPU, + FeatureBitset getFeatureBits(StringRef CPU, ArrayRef CPUTable, ArrayRef FeatureTable); diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp index ca3894b29d3..aed91c5cadf 100644 --- a/lib/MC/MCSubtargetInfo.cpp +++ b/lib/MC/MCSubtargetInfo.cpp @@ -63,14 +63,19 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS, /// ToggleFeature - Toggle a feature and returns the re-computed feature /// bits. This version does not change the implied bits. -uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) { +FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) { + FeatureBits.flip(FB); + return FeatureBits; +} + +FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) { FeatureBits ^= FB; return FeatureBits; } /// ToggleFeature - Toggle a feature and returns the re-computed feature /// bits. This version will also change all implied bits. -uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { +FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) { SubtargetFeatures Features; FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures); return FeatureBits; diff --git a/lib/MC/SubtargetFeature.cpp b/lib/MC/SubtargetFeature.cpp index 587be5427aa..2740839cd99 100644 --- a/lib/MC/SubtargetFeature.cpp +++ b/lib/MC/SubtargetFeature.cpp @@ -150,12 +150,12 @@ std::string SubtargetFeatures::getString() const { /// feature, set it. /// static -void SetImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry, +void SetImpliedBits(FeatureBitset &Bits, const SubtargetFeatureKV *FeatureEntry, ArrayRef FeatureTable) { for (auto &FE : FeatureTable) { if (FeatureEntry->Value == FE.Value) continue; - if (FeatureEntry->Implies & FE.Value) { + if ((FeatureEntry->Implies & FE.Value).any()) { Bits |= FE.Value; SetImpliedBits(Bits, &FE, FeatureTable); } @@ -166,12 +166,13 @@ void SetImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry, /// feature, clear it. /// static -void ClearImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry, +void ClearImpliedBits(FeatureBitset &Bits, + const SubtargetFeatureKV *FeatureEntry, ArrayRef FeatureTable) { for (auto &FE : FeatureTable) { if (FeatureEntry->Value == FE.Value) continue; - if (FE.Implies & FeatureEntry->Value) { + if ((FE.Implies & FeatureEntry->Value).any()) { Bits &= ~FE.Value; ClearImpliedBits(Bits, &FE, FeatureTable); } @@ -180,8 +181,8 @@ void ClearImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry, /// ToggleFeature - Toggle a feature and returns the newly updated feature /// bits. -uint64_t -SubtargetFeatures::ToggleFeature(uint64_t Bits, StringRef Feature, +FeatureBitset +SubtargetFeatures::ToggleFeature(FeatureBitset Bits, StringRef Feature, ArrayRef FeatureTable) { // Find feature in table. @@ -191,7 +192,6 @@ SubtargetFeatures::ToggleFeature(uint64_t Bits, StringRef Feature, if (FeatureEntry) { if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) { Bits &= ~FeatureEntry->Value; - // For each feature that implies this, clear it. ClearImpliedBits(Bits, FeatureEntry, FeatureTable); } else { @@ -212,13 +212,13 @@ SubtargetFeatures::ToggleFeature(uint64_t Bits, StringRef Feature, /// getFeatureBits - Get feature bits a CPU. /// -uint64_t +FeatureBitset SubtargetFeatures::getFeatureBits(StringRef CPU, ArrayRef CPUTable, ArrayRef FeatureTable) { if (CPUTable.empty() || FeatureTable.empty()) - return 0; + return FeatureBitset(); #ifndef NDEBUG for (size_t i = 1, e = CPUTable.size(); i != e; ++i) { @@ -230,7 +230,8 @@ SubtargetFeatures::getFeatureBits(StringRef CPU, "CPU features table is not sorted"); } #endif - uint64_t Bits = 0; // Resulting bits + // Resulting bits + FeatureBitset Bits; // Check if help is needed if (CPU == "help") @@ -247,7 +248,7 @@ SubtargetFeatures::getFeatureBits(StringRef CPU, // Set the feature implied by this CPU feature, if any. for (auto &FE : FeatureTable) { - if (CPUEntry->Value & FE.Value) + if ((CPUEntry->Value & FE.Value).any()) SetImpliedBits(Bits, &FE, FeatureTable); } } else { diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp index bc6c7a96f85..d127773283f 100644 --- a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp +++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp @@ -14,6 +14,7 @@ #include "llvm/ADT/APFloat.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/Regex.h" using namespace llvm; @@ -245,7 +246,7 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSPairs[] = { {"ich_elsr_el2", ICH_ELSR_EL2} }; -AArch64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits) +AArch64SysReg::MRSMapper::MRSMapper(const FeatureBitset &FeatureBits) : SysRegMapper(FeatureBits) { InstPairs = &MRSPairs[0]; NumInstPairs = llvm::array_lengthof(MRSPairs); @@ -269,7 +270,7 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRPairs[] = { {"icc_sgi0r_el1", ICC_SGI0R_EL1} }; -AArch64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits) +AArch64SysReg::MSRMapper::MSRMapper(const FeatureBitset &FeatureBits) : SysRegMapper(FeatureBits) { InstPairs = &MSRPairs[0]; NumInstPairs = llvm::array_lengthof(MSRPairs); @@ -773,7 +774,7 @@ AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const { } // Next search for target specific registers - if (FeatureBits & AArch64::ProcCyclone) { + if (FeatureBits[AArch64::ProcCyclone]) { for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) { if (CycloneSysRegPairs[i].Name == NameLower) { Valid = true; @@ -823,7 +824,7 @@ AArch64SysReg::SysRegMapper::toString(uint32_t Bits) const { } // Next search for target specific registers - if (FeatureBits & AArch64::ProcCyclone) { + if (FeatureBits[AArch64::ProcCyclone]) { for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) { if (CycloneSysRegPairs[i].Value == Bits) { return CycloneSysRegPairs[i].Name; diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/lib/Target/AArch64/Utils/AArch64BaseInfo.h index 6d0337ce15e..4e80a79d293 100644 --- a/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -26,6 +26,8 @@ namespace llvm { +class FeatureBitset; + inline static unsigned getWRegFromXReg(unsigned Reg) { switch (Reg) { case AArch64::X0: return AArch64::W0; @@ -1139,21 +1141,21 @@ namespace AArch64SysReg { const AArch64NamedImmMapper::Mapping *InstPairs; size_t NumInstPairs; - uint64_t FeatureBits; + const FeatureBitset &FeatureBits; - SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { } + SysRegMapper(const FeatureBitset &FeatureBits) : FeatureBits(FeatureBits) { } uint32_t fromString(StringRef Name, bool &Valid) const; std::string toString(uint32_t Bits) const; }; struct MSRMapper : SysRegMapper { static const AArch64NamedImmMapper::Mapping MSRPairs[]; - MSRMapper(uint64_t FeatureBits); + MSRMapper(const FeatureBitset &FeatureBits); }; struct MRSMapper : SysRegMapper { static const AArch64NamedImmMapper::Mapping MRSPairs[]; - MRSMapper(uint64_t FeatureBits); + MRSMapper(const FeatureBitset &FeatureBits); }; uint32_t ParseGenericRegister(StringRef Name, bool &Valid); diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 971e10df8b9..e21135c7cd3 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -420,7 +420,7 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, } static bool isThumb(const MCSubtargetInfo& STI) { - return (STI.getFeatureBits() & ARM::ModeThumb) != 0; + return STI.getFeatureBits()[ARM::ModeThumb]; } void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 7ee3cb0a3d1..1dfc6194406 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -4513,7 +4513,7 @@ breakPartialRegDependency(MachineBasicBlock::iterator MI, } bool ARMBaseInstrInfo::hasNOP() const { - return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0; + return Subtarget.getFeatureBits()[ARM::HasV6KOps]; } bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const { diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 3b0d787528d..a994869267e 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -263,8 +263,8 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { } // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default. - uint64_t Bits = getFeatureBits(); - if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters + const FeatureBitset &Bits = getFeatureBits(); + if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters (Options.UnsafeFPMath || isTargetDarwin())) UseNEONForSinglePrecisionFP = true; } diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index f7d397b7f02..61dde57015c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -244,37 +244,37 @@ class ARMAsmParser : public MCTargetAsmParser { bool isThumb() const { // FIXME: Can tablegen auto-generate this? - return (STI.getFeatureBits() & ARM::ModeThumb) != 0; + return STI.getFeatureBits()[ARM::ModeThumb]; } bool isThumbOne() const { - return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; + return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2]; } bool isThumbTwo() const { - return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); + return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2]; } bool hasThumb() const { - return STI.getFeatureBits() & ARM::HasV4TOps; + return STI.getFeatureBits()[ARM::HasV4TOps]; } bool hasV6Ops() const { - return STI.getFeatureBits() & ARM::HasV6Ops; + return STI.getFeatureBits()[ARM::HasV6Ops]; } bool hasV6MOps() const { - return STI.getFeatureBits() & ARM::HasV6MOps; + return STI.getFeatureBits()[ARM::HasV6MOps]; } bool hasV7Ops() const { - return STI.getFeatureBits() & ARM::HasV7Ops; + return STI.getFeatureBits()[ARM::HasV7Ops]; } bool hasV8Ops() const { - return STI.getFeatureBits() & ARM::HasV8Ops; + return STI.getFeatureBits()[ARM::HasV8Ops]; } bool hasARM() const { - return !(STI.getFeatureBits() & ARM::FeatureNoARM); + return !STI.getFeatureBits()[ARM::FeatureNoARM]; } bool hasThumb2DSP() const { - return STI.getFeatureBits() & ARM::FeatureDSPThumb2; + return STI.getFeatureBits()[ARM::FeatureDSPThumb2]; } bool hasD16() const { - return STI.getFeatureBits() & ARM::FeatureD16; + return STI.getFeatureBits()[ARM::FeatureD16]; } void SwitchMode() { @@ -282,7 +282,7 @@ class ARMAsmParser : public MCTargetAsmParser { setAvailableFeatures(FB); } bool isMClass() const { - return STI.getFeatureBits() & ARM::FeatureMClass; + return STI.getFeatureBits()[ARM::FeatureMClass]; } /// @name Auto-generated Match Functions @@ -9186,52 +9186,53 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { // tools/clang/lib/Driver/Tools.cpp static const struct { const unsigned ID; - const uint64_t Enabled; - const uint64_t Disabled; + const FeatureBitset Enabled; + const FeatureBitset Disabled; } FPUs[] = { - {/* ID */ ARM::VFP, - /* Enabled */ ARM::FeatureVFP2, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::VFPV2, - /* Enabled */ ARM::FeatureVFP2, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::VFPV3, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16}, - {/* ID */ ARM::VFPV3_D16, - /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::VFPV4, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16}, - {/* ID */ ARM::VFPV4_D16, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureD16, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::FPV5_D16, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8 | ARM::FeatureD16, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto}, - {/* ID */ ARM::FP_ARMV8, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16}, - {/* ID */ ARM::NEON, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON, - /* Disabled */ ARM::FeatureD16}, - {/* ID */ ARM::NEON_VFPV4, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureNEON, - /* Disabled */ ARM::FeatureD16}, - {/* ID */ ARM::NEON_FP_ARMV8, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8 | ARM::FeatureNEON, - /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16}, - {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, - /* Disabled */ ARM::FeatureD16}, - {ARM::SOFTVFP, 0, 0}, + {/* ID */ ARM::VFP, + /* Enabled */ {ARM::FeatureVFP2}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::VFPV2, + /* Enabled */ {ARM::FeatureVFP2}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::VFPV3, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}}, + {/* ID */ ARM::VFPV3_D16, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureD16}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::VFPV4, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}}, + {/* ID */ ARM::VFPV4_D16, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureD16}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::FPV5_D16, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8, ARM::FeatureD16}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto}}, + {/* ID */ ARM::FP_ARMV8, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto, ARM::FeatureD16}}, + {/* ID */ ARM::NEON, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON}, + /* Disabled */ {ARM::FeatureD16}}, + {/* ID */ ARM::NEON_VFPV4, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureNEON}, + /* Disabled */ {ARM::FeatureD16}}, + {/* ID */ ARM::NEON_FP_ARMV8, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8, ARM::FeatureNEON}, + /* Disabled */ {ARM::FeatureCrypto, ARM::FeatureD16}}, + {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8, ARM::FeatureNEON, + ARM::FeatureCrypto}, + /* Disabled */ {ARM::FeatureD16}}, + {ARM::SOFTVFP, {}, {}}, }; /// parseDirectiveFPU @@ -9256,8 +9257,8 @@ bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { // Need to toggle features that should be on but are off and that // should off but are on. - uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) | - (Entry.Disabled & STI.getFeatureBits()); + FeatureBitset Toggle = (Entry.Enabled & ~STI.getFeatureBits()) | + (Entry.Disabled & STI.getFeatureBits()); setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle))); break; } @@ -9994,30 +9995,30 @@ extern "C" void LLVMInitializeARMAsmParser() { static const struct { const char *Name; const unsigned ArchCheck; - const uint64_t Features; + const FeatureBitset Features; } Extensions[] = { - { "crc", Feature_HasV8, ARM::FeatureCRC }, + { "crc", Feature_HasV8, {ARM::FeatureCRC} }, { "crypto", Feature_HasV8, - ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 }, - { "fp", Feature_HasV8, ARM::FeatureFPARMv8 }, + {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} }, + { "fp", Feature_HasV8, {ARM::FeatureFPARMv8} }, { "idiv", Feature_HasV7 | Feature_IsNotMClass, - ARM::FeatureHWDiv | ARM::FeatureHWDivARM }, + {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} }, // FIXME: iWMMXT not supported - { "iwmmxt", Feature_None, 0 }, + { "iwmmxt", Feature_None, {} }, // FIXME: iWMMXT2 not supported - { "iwmmxt2", Feature_None, 0 }, + { "iwmmxt2", Feature_None, {} }, // FIXME: Maverick not supported - { "maverick", Feature_None, 0 }, - { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP }, + { "maverick", Feature_None, {} }, + { "mp", Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} }, // FIXME: ARMv6-m OS Extensions feature not checked - { "os", Feature_None, 0 }, + { "os", Feature_None, {} }, // FIXME: Also available in ARMv6-K - { "sec", Feature_HasV7, ARM::FeatureTrustZone }, - { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 }, + { "sec", Feature_HasV7, {ARM::FeatureTrustZone} }, + { "simd", Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} }, // FIXME: Only available in A-class, isel not predicated - { "virt", Feature_HasV7, ARM::FeatureVirtualization }, + { "virt", Feature_HasV7, {ARM::FeatureVirtualization} }, // FIXME: xscale not supported - { "xscale", Feature_None, 0 }, + { "xscale", Feature_None, {} }, }; /// parseDirectiveArchExtension @@ -10045,7 +10046,7 @@ bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { if (Extension.Name != Name) continue; - if (!Extension.Features) + if (Extension.Features.none()) report_fatal_error("unsupported architectural extension: " + Name); if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) { @@ -10054,9 +10055,10 @@ bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { return false; } - uint64_t ToggleFeatures = EnableFeature - ? (~STI.getFeatureBits() & Extension.Features) - : ( STI.getFeatureBits() & Extension.Features); + FeatureBitset ToggleFeatures = EnableFeature + ? (~STI.getFeatureBits() & Extension.Features) + : ( STI.getFeatureBits() & Extension.Features); + uint64_t Features = ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); setAvailableFeatures(Features); diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 4d5122a7620..bd04422f67f 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -431,7 +431,7 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, raw_ostream &CS) const { CommentStream = &CS; - assert(!(STI.getFeatureBits() & ARM::ModeThumb) && + assert(!STI.getFeatureBits()[ARM::ModeThumb] && "Asked to disassemble an ARM instruction but Subtarget is in Thumb " "mode!"); @@ -696,7 +696,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, raw_ostream &CS) const { CommentStream = &CS; - assert((STI.getFeatureBits() & ARM::ModeThumb) && + assert(STI.getFeatureBits()[ARM::ModeThumb] && "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); // We want to read exactly 2 bytes of data. @@ -1022,9 +1022,10 @@ static const uint16_t DPRDecoderTable[] = { static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasD16 = featureBits & ARM::FeatureD16; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasD16 = featureBits[ARM::FeatureD16]; if (RegNo > 31 || (hasD16 && RegNo > 15)) return MCDisassembler::Fail; @@ -1369,9 +1370,9 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, break; } - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + if (featureBits[ARM::HasV8Ops] && (coproc != 14)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(coproc)); @@ -3267,10 +3268,11 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = featureBits & ARM::FeatureMP; - bool hasV7Ops = featureBits & ARM::HasV7Ops; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3353,10 +3355,11 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, imm |= (Rn << 9); unsigned add = fieldFromInstruction(Insn, 9, 1); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = featureBits & ARM::FeatureMP; - bool hasV7Ops = featureBits & ARM::HasV7Ops; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3433,10 +3436,11 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, unsigned imm = fieldFromInstruction(Insn, 0, 12); imm |= (Rn << 13); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = (featureBits & ARM::FeatureMP); - bool hasV7Ops = (featureBits & ARM::HasV7Ops); + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3550,9 +3554,10 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, unsigned U = fieldFromInstruction(Insn, 23, 1); int imm = fieldFromInstruction(Insn, 0, 12); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasV7Ops = (featureBits & ARM::HasV7Ops); + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rt == 15) { switch (Inst.getOpcode()) { @@ -3873,9 +3878,10 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, if (Val == 0xA || Val == 0xB) return MCDisassembler::Fail; - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(Val)); @@ -4025,9 +4031,10 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; - uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if (FeatureBits & ARM::FeatureMClass) { + const FeatureBitset &FeatureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + if (FeatureBits[ARM::FeatureMClass]) { unsigned ValLow = Val & 0xff; // Validate the SYSm value first. @@ -4047,7 +4054,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, case 17: // basepri case 18: // basepri_max case 19: // faultmask - if (!(FeatureBits & ARM::HasV7Ops)) + if (!(FeatureBits[ARM::HasV7Ops])) // Values basepri, basepri_max and faultmask are only valid for v7m. return MCDisassembler::Fail; break; @@ -4057,7 +4064,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, if (Inst.getOpcode() == ARM::t2MSR_M) { unsigned Mask = fieldFromInstruction(Val, 10, 2); - if (!(FeatureBits & ARM::HasV7Ops)) { + if (!(FeatureBits[ARM::HasV7Ops])) { // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are // unpredictable. if (Mask != 2) @@ -4071,7 +4078,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, // indicates the move for the GE{3:0} bits, the mask{0} bit can be set // only if the processor includes the DSP extension. if (Mask == 0 || (Mask != 2 && ValLow > 3) || - (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) + (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1))) S = MCDisassembler::SoftFail; } } diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 16eea335261..41287df8276 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -90,7 +90,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, case 3: O << "\twfi"; break; case 4: O << "\tsev"; break; case 5: - if ((getAvailableFeatures() & ARM::HasV8Ops)) { + if (getAvailableFeatures()[ARM::HasV8Ops]) { O << "\tsevl"; break; } // Fallthrough for non-v8 @@ -299,7 +299,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() && MI->getOperand(0).getImm() == 0 && - (getAvailableFeatures() & ARM::FeatureVirtualization)) { + getAvailableFeatures()[ARM::FeatureVirtualization]) { O << "\teret"; printPredicateOperand(MI, 1, O); printAnnotation(O, Annot); @@ -698,7 +698,7 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O) { unsigned val = MI->getOperand(OpNum).getImm(); - O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops)); + O << ARM_MB::MemBOptToString(val, getAvailableFeatures()[ARM::HasV8Ops]); } void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum, @@ -796,14 +796,14 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCOperand &Op = MI->getOperand(OpNum); unsigned SpecRegRBit = Op.getImm() >> 4; unsigned Mask = Op.getImm() & 0xf; - uint64_t FeatureBits = getAvailableFeatures(); + const FeatureBitset &FeatureBits = getAvailableFeatures(); - if (FeatureBits & ARM::FeatureMClass) { + if (FeatureBits[ARM::FeatureMClass]) { unsigned SYSm = Op.getImm(); unsigned Opcode = MI->getOpcode(); // For writes, handle extended mask bits if the DSP extension is present. - if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) { + if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) { switch (SYSm) { case 0x400: O << "apsr_g"; return; case 0xc00: O << "apsr_nzcvqg"; return; @@ -819,7 +819,7 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, // Handle the basic 8-bit mask. SYSm &= 0xff; - if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) { + if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { // ARMv7-M deprecates using MSR APSR without a _ qualifier as an // alias for MSR APSR_nzcvq. switch (SYSm) { diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h index f4f10821037..1246cc46a60 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -33,7 +33,7 @@ public: return ARM::NumTargetFixupKinds; } - bool hasNOP() const { return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; } + bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index e48cabbf7ee..4d1bec33401 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -51,10 +51,10 @@ public: ~ARMMCCodeEmitter() {} bool isThumb(const MCSubtargetInfo &STI) const { - return (STI.getFeatureBits() & ARM::ModeThumb) != 0; + return STI.getFeatureBits()[ARM::ModeThumb]; } bool isThumb2(const MCSubtargetInfo &STI) const { - return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; + return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; } bool isTargetMachO(const MCSubtargetInfo &STI) const { Triple TT(STI.getTargetTriple()); diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 82dac5c4357..3ecd559348a 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -33,7 +33,7 @@ using namespace llvm; static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - if (STI.getFeatureBits() & llvm::ARM::HasV7Ops && + if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && // Checks for the deprecated CP15ISB encoding: @@ -65,7 +65,7 @@ static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() && + if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) { Info = "applying IT instruction to more than one subsequent instruction is " "deprecated"; @@ -77,7 +77,7 @@ static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) && + assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && "cannot predicate thumb instructions"); assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); @@ -94,7 +94,7 @@ static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) && + assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && "cannot predicate thumb instructions"); assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index a502466338b..7f3858a22ad 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -72,15 +72,7 @@ public: // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]). // The reason we need this mask is explained in the selectArch function. // FIXME: Ideally we would like TableGen to generate this information. - static const uint64_t AllArchRelatedMask = - Mips::FeatureMips1 | Mips::FeatureMips2 | Mips::FeatureMips3 | - Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 | - Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 | - Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 | - Mips::FeatureMips32r3 | Mips::FeatureMips32r5 | Mips::FeatureMips32r6 | - Mips::FeatureMips64 | Mips::FeatureMips64r2 | Mips::FeatureMips64r3 | - Mips::FeatureMips64r5 | Mips::FeatureMips64r6 | Mips::FeatureCnMips | - Mips::FeatureFP64Bit | Mips::FeatureGP64Bit | Mips::FeatureNaN2008; + static const FeatureBitset AllArchRelatedMask; private: unsigned ATReg; @@ -90,6 +82,17 @@ private: }; } +const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = { + Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3, + Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4, + Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5, + Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2, + Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6, + Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3, + Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips, + Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008 +}; + namespace { class MipsAsmParser : public MCTargetAsmParser { MipsTargetStreamer &getTargetStreamer() { @@ -299,7 +302,7 @@ class MipsAsmParser : public MCTargetAsmParser { // FeatureMipsGP64 | FeatureMips1) // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4). void selectArch(StringRef ArchFeature) { - uint64_t FeatureBits = STI.getFeatureBits(); + FeatureBitset FeatureBits = STI.getFeatureBits(); FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; STI.setFeatureBits(FeatureBits); setAvailableFeatures( @@ -308,7 +311,7 @@ class MipsAsmParser : public MCTargetAsmParser { } void setFeatureBits(uint64_t Feature, StringRef FeatureString) { - if (!(STI.getFeatureBits() & Feature)) { + if (!(STI.getFeatureBits()[Feature])) { setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); } @@ -316,7 +319,7 @@ class MipsAsmParser : public MCTargetAsmParser { } void clearFeatureBits(uint64_t Feature, StringRef FeatureString) { - if (STI.getFeatureBits() & Feature) { + if (STI.getFeatureBits()[Feature]) { setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); } @@ -361,65 +364,66 @@ public: /// True if all of $fcc0 - $fcc7 exist for the current ISA. bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); } - bool isGP64bit() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } - bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit; } + bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } + bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } const MipsABIInfo &getABI() const { return ABI; } bool isABI_N32() const { return ABI.IsN32(); } bool isABI_N64() const { return ABI.IsN64(); } bool isABI_O32() const { return ABI.IsO32(); } - bool isABI_FPXX() const { return STI.getFeatureBits() & Mips::FeatureFPXX; } + bool isABI_FPXX() const { return STI.getFeatureBits()[Mips::FeatureFPXX]; } bool useOddSPReg() const { - return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg); + return !(STI.getFeatureBits()[Mips::FeatureNoOddSPReg]); } bool inMicroMipsMode() const { - return STI.getFeatureBits() & Mips::FeatureMicroMips; + return STI.getFeatureBits()[Mips::FeatureMicroMips]; } - bool hasMips1() const { return STI.getFeatureBits() & Mips::FeatureMips1; } - bool hasMips2() const { return STI.getFeatureBits() & Mips::FeatureMips2; } - bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } - bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; } - bool hasMips5() const { return STI.getFeatureBits() & Mips::FeatureMips5; } + bool hasMips1() const { return STI.getFeatureBits()[Mips::FeatureMips1]; } + bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } + bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } + bool hasMips4() const { return STI.getFeatureBits()[Mips::FeatureMips4]; } + bool hasMips5() const { return STI.getFeatureBits()[Mips::FeatureMips5]; } bool hasMips32() const { - return (STI.getFeatureBits() & Mips::FeatureMips32); + return STI.getFeatureBits()[Mips::FeatureMips32]; } bool hasMips64() const { - return (STI.getFeatureBits() & Mips::FeatureMips64); + return STI.getFeatureBits()[Mips::FeatureMips64]; } bool hasMips32r2() const { - return (STI.getFeatureBits() & Mips::FeatureMips32r2); + return STI.getFeatureBits()[Mips::FeatureMips32r2]; } bool hasMips64r2() const { - return (STI.getFeatureBits() & Mips::FeatureMips64r2); + return STI.getFeatureBits()[Mips::FeatureMips64r2]; } bool hasMips32r3() const { - return (STI.getFeatureBits() & Mips::FeatureMips32r3); + return (STI.getFeatureBits()[Mips::FeatureMips32r3]); } bool hasMips64r3() const { - return (STI.getFeatureBits() & Mips::FeatureMips64r3); + return (STI.getFeatureBits()[Mips::FeatureMips64r3]); } bool hasMips32r5() const { - return (STI.getFeatureBits() & Mips::FeatureMips32r5); + return (STI.getFeatureBits()[Mips::FeatureMips32r5]); } bool hasMips64r5() const { - return (STI.getFeatureBits() & Mips::FeatureMips64r5); + return (STI.getFeatureBits()[Mips::FeatureMips64r5]); } bool hasMips32r6() const { - return (STI.getFeatureBits() & Mips::FeatureMips32r6); + return STI.getFeatureBits()[Mips::FeatureMips32r6]; } bool hasMips64r6() const { - return (STI.getFeatureBits() & Mips::FeatureMips64r6); + return STI.getFeatureBits()[Mips::FeatureMips64r6]; } + + bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; } + bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; } + bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; } bool hasCnMips() const { - return (STI.getFeatureBits() & Mips::FeatureCnMips); + return (STI.getFeatureBits()[Mips::FeatureCnMips]); } - bool hasDSP() const { return (STI.getFeatureBits() & Mips::FeatureDSP); } - bool hasDSPR2() const { return (STI.getFeatureBits() & Mips::FeatureDSPR2); } - bool hasMSA() const { return (STI.getFeatureBits() & Mips::FeatureMSA); } bool inMips16Mode() const { - return STI.getFeatureBits() & Mips::FeatureMips16; + return STI.getFeatureBits()[Mips::FeatureMips16]; } // TODO: see how can we get this info. bool abiUsesSoftFloat() const { return false; } diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 8849366e837..c69a60b5d21 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -36,16 +36,16 @@ class MipsDisassembler : public MCDisassembler { public: MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) : MCDisassembler(STI, Ctx), - IsMicroMips(STI.getFeatureBits() & Mips::FeatureMicroMips), + IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), IsBigEndian(IsBigEndian) {} - bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } - bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } + bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } + bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } bool hasMips32r6() const { - return STI.getFeatureBits() & Mips::FeatureMips32r6; + return STI.getFeatureBits()[Mips::FeatureMips32r6]; } - bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } + bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } bool hasCOP3() const { // Only present in MIPS-I and MIPS-II diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 1c2f2da6c96..152399a0d68 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -112,7 +112,7 @@ static void LowerDextDins(MCInst& InstIn) { } bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { - return STI.getFeatureBits() & Mips::FeatureMicroMips; + return STI.getFeatureBits()[Mips::FeatureMicroMips]; } void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { @@ -175,7 +175,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, (Opcode != Mips::SLL_MM) && !Binary) llvm_unreachable("unimplemented opcode in EncodeInstruction()"); - if (STI.getFeatureBits() & Mips::FeatureMicroMips) { + if (STI.getFeatureBits()[Mips::FeatureMicroMips]) { int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); if (NewOpcode != -1) { if (Fixups.size() > N) diff --git a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index e6d29673461..a832698360e 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -382,7 +382,7 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, ? true : false; - uint64_t Features = STI.getFeatureBits(); + const FeatureBitset &Features = STI.getFeatureBits(); // Set the header flags that we can in the constructor. // FIXME: This is a fairly terrible hack. We set the rest @@ -398,35 +398,35 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, unsigned EFlags = MCA.getELFHeaderEFlags(); // Architecture - if (Features & Mips::FeatureMips64r6) + if (Features[Mips::FeatureMips64r6]) EFlags |= ELF::EF_MIPS_ARCH_64R6; - else if (Features & Mips::FeatureMips64r2 || - Features & Mips::FeatureMips64r3 || - Features & Mips::FeatureMips64r5) + else if (Features[Mips::FeatureMips64r2] || + Features[Mips::FeatureMips64r3] || + Features[Mips::FeatureMips64r5]) EFlags |= ELF::EF_MIPS_ARCH_64R2; - else if (Features & Mips::FeatureMips64) + else if (Features[Mips::FeatureMips64]) EFlags |= ELF::EF_MIPS_ARCH_64; - else if (Features & Mips::FeatureMips5) + else if (Features[Mips::FeatureMips5]) EFlags |= ELF::EF_MIPS_ARCH_5; - else if (Features & Mips::FeatureMips4) + else if (Features[Mips::FeatureMips4]) EFlags |= ELF::EF_MIPS_ARCH_4; - else if (Features & Mips::FeatureMips3) + else if (Features[Mips::FeatureMips3]) EFlags |= ELF::EF_MIPS_ARCH_3; - else if (Features & Mips::FeatureMips32r6) + else if (Features[Mips::FeatureMips32r6]) EFlags |= ELF::EF_MIPS_ARCH_32R6; - else if (Features & Mips::FeatureMips32r2 || - Features & Mips::FeatureMips32r3 || - Features & Mips::FeatureMips32r5) + else if (Features[Mips::FeatureMips32r2] || + Features[Mips::FeatureMips32r3] || + Features[Mips::FeatureMips32r5]) EFlags |= ELF::EF_MIPS_ARCH_32R2; - else if (Features & Mips::FeatureMips32) + else if (Features[Mips::FeatureMips32]) EFlags |= ELF::EF_MIPS_ARCH_32; - else if (Features & Mips::FeatureMips2) + else if (Features[Mips::FeatureMips2]) EFlags |= ELF::EF_MIPS_ARCH_2; else EFlags |= ELF::EF_MIPS_ARCH_1; // Other options. - if (Features & Mips::FeatureNaN2008) + if (Features[Mips::FeatureNaN2008]) EFlags |= ELF::EF_MIPS_NAN2008; // -mabicalls and -mplt are not implemented but we should act as if they were @@ -466,7 +466,7 @@ void MipsTargetELFStreamer::finish() { DataSectionData.setAlignment(std::max(16u, DataSectionData.getAlignment())); BSSSectionData.setAlignment(std::max(16u, BSSSectionData.getAlignment())); - uint64_t Features = STI.getFeatureBits(); + const FeatureBitset &Features = STI.getFeatureBits(); // Update e_header flags. See the FIXME and comment above in // the constructor for a full rundown on this. @@ -479,10 +479,10 @@ void MipsTargetELFStreamer::finish() { else if (getABI().IsN32()) EFlags |= ELF::EF_MIPS_ABI2; - if (Features & Mips::FeatureGP64Bit) { + if (Features[Mips::FeatureGP64Bit]) { if (getABI().IsO32()) EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */ - } else if (Features & Mips::FeatureMips64r2 || Features & Mips::FeatureMips64) + } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64]) EFlags |= ELF::EF_MIPS_32BITMODE; // If we've set the cpic eflag and we're n64, go ahead and set the pic diff --git a/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 0ed07239327..605e74bf642 100644 --- a/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -355,7 +355,7 @@ DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, uint32_t Inst = (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0); - if ((STI.getFeatureBits() & PPC::FeatureQPX) != 0) { + if (STI.getFeatureBits()[PPC::FeatureQPX]) { DecodeStatus result = decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); if (result != MCDisassembler::Fail) diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp index fa25f590f23..404663416f5 100644 --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp @@ -99,7 +99,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, } else if (IS_VTX(Desc)) { uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset - if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) { + if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) { InstWord2 |= 1 << 19; // Mega-Fetch bit } @@ -132,7 +132,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, Emit((uint32_t) 0, OS); } else { uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); - if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && + if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) && ((Desc.TSFlags & R600_InstFlag::OP1) || Desc.TSFlags & R600_InstFlag::OP2)) { uint64_t ISAOpCode = Inst & (0x3FFULL << 39); diff --git a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp index 5975a517994..dc9fb1ac51f 100644 --- a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp +++ b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp @@ -35,7 +35,7 @@ namespace Sparc { #include "SparcGenAsmWriter.inc" bool SparcInstPrinter::isV9() const { - return (STI.getFeatureBits() & Sparc::FeatureV9) != 0; + return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; } void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const diff --git a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp index 543af8e4e77..ed31a58d7ff 100644 --- a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp +++ b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp @@ -262,13 +262,13 @@ protected: MCContext &Ctx, int64_t *Residue); bool is64BitMode() const { - return (STI.getFeatureBits() & X86::Mode64Bit) != 0; + return STI.getFeatureBits()[X86::Mode64Bit]; } bool is32BitMode() const { - return (STI.getFeatureBits() & X86::Mode32Bit) != 0; + return STI.getFeatureBits()[X86::Mode32Bit]; } bool is16BitMode() const { - return (STI.getFeatureBits() & X86::Mode16Bit) != 0; + return STI.getFeatureBits()[X86::Mode16Bit]; } unsigned getPointerWidth() { @@ -1073,9 +1073,9 @@ CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const bool hasCompilerRTSupport = T.isOSLinux(); if (ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions.SanitizeAddress) { - if ((STI.getFeatureBits() & X86::Mode32Bit) != 0) + if (STI.getFeatureBits()[X86::Mode32Bit] != 0) return new X86AddressSanitizer32(STI); - if ((STI.getFeatureBits() & X86::Mode64Bit) != 0) + if (STI.getFeatureBits()[X86::Mode64Bit] != 0) return new X86AddressSanitizer64(STI); } return new X86AsmInstrumentation(STI); diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index c24805a6543..59d0c1a89bb 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -729,23 +729,24 @@ private: bool is64BitMode() const { // FIXME: Can tablegen auto-generate this? - return (STI.getFeatureBits() & X86::Mode64Bit) != 0; + return STI.getFeatureBits()[X86::Mode64Bit]; } bool is32BitMode() const { // FIXME: Can tablegen auto-generate this? - return (STI.getFeatureBits() & X86::Mode32Bit) != 0; + return STI.getFeatureBits()[X86::Mode32Bit]; } bool is16BitMode() const { // FIXME: Can tablegen auto-generate this? - return (STI.getFeatureBits() & X86::Mode16Bit) != 0; + return STI.getFeatureBits()[X86::Mode16Bit]; } - void SwitchMode(uint64_t mode) { - uint64_t oldMode = STI.getFeatureBits() & - (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit); - unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode)); + void SwitchMode(unsigned mode) { + FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit}); + FeatureBitset OldMode = STI.getFeatureBits() & AllModes; + unsigned FB = ComputeAvailableFeatures( + STI.ToggleFeature(OldMode.flip(mode))); setAvailableFeatures(FB); - assert(mode == (STI.getFeatureBits() & - (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit))); + + assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes)); } unsigned getPointerWidth() { @@ -1688,7 +1689,7 @@ std::unique_ptr X86AsmParser::ParseIntelOperand() { } // rounding mode token - if (STI.getFeatureBits() & X86::FeatureAVX512 && + if (STI.getFeatureBits()[X86::FeatureAVX512] && getLexer().is(AsmToken::LCurly)) return ParseRoundingModeOp(Start, End); @@ -1746,7 +1747,7 @@ std::unique_ptr X86AsmParser::ParseATTOperand() { } case AsmToken::LCurly:{ SMLoc Start = Parser.getTok().getLoc(), End; - if (STI.getFeatureBits() & X86::FeatureAVX512) + if (STI.getFeatureBits()[X86::FeatureAVX512]) return ParseRoundingModeOp(Start, End); return ErrorOperand(Start, "unknown token in expression"); } @@ -1756,7 +1757,7 @@ std::unique_ptr X86AsmParser::ParseATTOperand() { bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands, const MCParsedAsmOperand &Op) { MCAsmParser &Parser = getParser(); - if(STI.getFeatureBits() & X86::FeatureAVX512) { + if(STI.getFeatureBits()[X86::FeatureAVX512]) { if (getLexer().is(AsmToken::LCurly)) { // Eat "{" and mark the current place. const SMLoc consumedToken = consumeToken(); diff --git a/lib/Target/X86/Disassembler/X86Disassembler.cpp b/lib/Target/X86/Disassembler/X86Disassembler.cpp index e8c547517b0..46a6b3c8b2e 100644 --- a/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -80,20 +80,19 @@ X86GenericDisassembler::X86GenericDisassembler( MCContext &Ctx, std::unique_ptr MII) : MCDisassembler(STI, Ctx), MII(std::move(MII)) { - switch (STI.getFeatureBits() & - (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) { - case X86::Mode16Bit: + const FeatureBitset &FB = STI.getFeatureBits(); + if (FB[X86::Mode16Bit]) { fMode = MODE_16BIT; - break; - case X86::Mode32Bit: + return; + } else if (FB[X86::Mode32Bit]) { fMode = MODE_32BIT; - break; - case X86::Mode64Bit: + return; + } else if (FB[X86::Mode64Bit]) { fMode = MODE_64BIT; - break; - default: - llvm_unreachable("Invalid CPU mode"); + return; } + + llvm_unreachable("Invalid CPU mode"); } struct Region { diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp index 65461af5b7b..ec2dc87398d 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -60,7 +60,7 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, // InstrInfo.td as soon as Requires clause is supported properly // for InstAlias. if (MI->getOpcode() == X86::CALLpcrel32 && - (getAvailableFeatures() & X86::Mode64Bit) != 0) { + getAvailableFeatures()[X86::Mode64Bit]) { OS << "\tcallq\t"; printPCRelImm(MI, 0, OS); } diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 9b98a3e40d4..7124501f979 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -42,15 +42,15 @@ public: ~X86MCCodeEmitter() {} bool is64BitMode(const MCSubtargetInfo &STI) const { - return (STI.getFeatureBits() & X86::Mode64Bit) != 0; + return STI.getFeatureBits()[X86::Mode64Bit]; } bool is32BitMode(const MCSubtargetInfo &STI) const { - return (STI.getFeatureBits() & X86::Mode32Bit) != 0; + return STI.getFeatureBits()[X86::Mode32Bit]; } bool is16BitMode(const MCSubtargetInfo &STI) const { - return (STI.getFeatureBits() & X86::Mode16Bit) != 0; + return STI.getFeatureBits()[X86::Mode16Bit]; } /// Is16BitMemOperand - Return true if the specified instruction has diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index 159bc23fbff..65d930ad858 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -2248,7 +2248,7 @@ static void emitComputeAvailableFeatures(AsmMatcherInfo &Info, Info.AsmParser->getValueAsString("AsmParserClassName"); OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n" - << "ComputeAvailableFeatures(uint64_t FB) const {\n"; + << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n"; OS << " uint64_t Features = 0;\n"; for (const auto &SF : Info.SubtargetFeatures) { const SubtargetFeatureInfo &SFI = SF.second; @@ -2270,12 +2270,10 @@ static void emitComputeAvailableFeatures(AsmMatcherInfo &Info, Cond = Cond.substr(1); } - OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")"; + OS << "("; if (Neg) - OS << " == 0"; - else - OS << " != 0"; - OS << ")"; + OS << "!"; + OS << "FB[" << Info.Target.getName() << "::" << Cond << "])"; if (Comma.second.empty()) break; @@ -2645,7 +2643,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << "#undef GET_ASSEMBLER_HEADER\n"; OS << " // This should be included into the middle of the declaration of\n"; OS << " // your subclasses implementation of MCTargetAsmParser.\n"; - OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; + OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n"; OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, " << "unsigned Opcode,\n" << " const OperandVector " diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp index c69b89b9bc0..30812fb9548 100644 --- a/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -848,7 +848,7 @@ emitPredicateFunction(formatted_raw_ostream &OS, PredicateSet &Predicates, // The predicate function is just a big switch statement based on the // input predicate index. OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, " - << "uint64_t Bits) {\n"; + << "const FeatureBitset& Bits) {\n"; Indentation += 2; if (!Predicates.empty()) { OS.indent(Indentation) << "switch (Idx) {\n"; @@ -1102,10 +1102,10 @@ unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders, static void emitSinglePredicateMatch(raw_ostream &o, StringRef str, const std::string &PredicateNamespace) { if (str[0] == '!') - o << "!(Bits & " << PredicateNamespace << "::" - << str.slice(1,str.size()) << ")"; + o << "!Bits[" << PredicateNamespace << "::" + << str.slice(1,str.size()) << "]"; else - o << "(Bits & " << PredicateNamespace << "::" << str << ")"; + o << "Bits[" << PredicateNamespace << "::" << str << "]"; } bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, @@ -2010,7 +2010,7 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) { << " InsnType insn, uint64_t Address,\n" << " const void *DisAsm,\n" << " const MCSubtargetInfo &STI) {\n" - << " uint64_t Bits = STI.getFeatureBits();\n" + << " const FeatureBitset& Bits = STI.getFeatureBits();\n" << "\n" << " const uint8_t *Ptr = DecodeTable;\n" << " uint32_t CurFieldValue = 0;\n" diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index f999326bc97..798c407e900 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -549,15 +549,15 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, CodeGenTarget &Target = CDP.getTargetInfo(); if (Inst.HasComplexDeprecationPredicate) // Emit a function pointer to the complex predicate method. - OS << ",0" + OS << ", { } " << ",&get" << Inst.DeprecatedReason << "DeprecationInfo"; else if (!Inst.DeprecatedReason.empty()) // Emit the Subtarget feature. - OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason - << ",nullptr"; + OS << ", { " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason + << "} ,nullptr"; else // Instruction isn't deprecated. - OS << ",0,nullptr"; + OS << ", { } ,nullptr"; OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; } diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index e5c62fa1375..831a7732ee4 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -16,6 +16,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/MC/MCInstrItineraries.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Format.h" #include "llvm/TableGen/Error.h" @@ -62,7 +63,7 @@ class SubtargetEmitter { CodeGenSchedModels &SchedModels; std::string Target; - void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits); + void Enumeration(raw_ostream &OS, const char *ClassName); unsigned FeatureKeyValues(raw_ostream &OS); unsigned CPUKeyValues(raw_ostream &OS); void FormItineraryStageString(const std::string &Names, @@ -112,8 +113,7 @@ public: // Enumeration - Emit the specified class as an enumeration. // void SubtargetEmitter::Enumeration(raw_ostream &OS, - const char *ClassName, - bool isBits) { + const char *ClassName) { // Get all records of class and sort std::vector DefList = Records.getAllDerivedDefinitions(ClassName); std::sort(DefList.begin(), DefList.end(), LessRecord()); @@ -121,8 +121,8 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS, unsigned N = DefList.size(); if (N == 0) return; - if (N > 64) { - errs() << "Too many (> 64) subtarget features!\n"; + if (N > MAX_SUBTARGET_FEATURES) { + errs() << "Too many subtarget features! Bump MAX_SUBTARGET_FEATURES."; exit(1); } @@ -137,21 +137,14 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS, Record *Def = DefList[i]; // Get and emit name - OS << " " << Def->getName(); - - // If bit flags then emit expression (1 << i) - if (isBits) OS << " = " << " 1ULL << " << i; - - // Depending on 'if more in the list' emit comma + OS << " " << Def->getName() << " = " << i; if (++i < N) OS << ","; OS << "\n"; } - // Close enumeration - OS << "};\n"; - - OS << "}\n"; + // Close enumeration and namespace + OS << "};\n}\n"; } // @@ -185,22 +178,24 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { if (CommandLineName.empty()) continue; - // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in } + // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in } } OS << " { " << "\"" << CommandLineName << "\", " << "\"" << Desc << "\", " - << Target << "::" << Name << ", "; + << "{ " << Target << "::" << Name << " }, "; const std::vector &ImpliesList = Feature->getValueAsListOfDefs("Implies"); if (ImpliesList.empty()) { - OS << "0ULL"; + OS << "{ }"; } else { + OS << "{ "; for (unsigned j = 0, M = ImpliesList.size(); j < M;) { OS << Target << "::" << ImpliesList[j]->getName(); - if (++j < M) OS << " | "; + if (++j < M) OS << ", "; } + OS << " }"; } OS << " }"; @@ -242,22 +237,24 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { const std::vector &FeatureList = Processor->getValueAsListOfDefs("Features"); - // Emit as { "cpu", "description", f1 | f2 | ... fn }, + // Emit as { "cpu", "description", { f1 , f2 , ... fn } }, OS << " { " << "\"" << Name << "\", " << "\"Select the " << Name << " processor\", "; if (FeatureList.empty()) { - OS << "0ULL"; + OS << "{ }"; } else { + OS << "{ "; for (unsigned j = 0, M = FeatureList.size(); j < M;) { OS << Target << "::" << FeatureList[j]->getName(); - if (++j < M) OS << " | "; + if (++j < M) OS << ", "; } + OS << " }"; } - // The "0" is for the "implies" section of this data structure. - OS << ", 0ULL }"; + // The { } is for the "implies" section of this data structure. + OS << ", { } }"; // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; @@ -1385,7 +1382,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS, } OS << " InitMCProcessorInfo(CPU, FS);\n" - << " uint64_t Bits = getFeatureBits();\n"; + << " const FeatureBitset& Bits = getFeatureBits();\n"; for (unsigned i = 0; i < Features.size(); i++) { // Next record @@ -1395,12 +1392,12 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS, const std::string &Attribute = R->getValueAsString("Attribute"); if (Value=="true" || Value=="false") - OS << " if ((Bits & " << Target << "::" - << Instance << ") != 0) " + OS << " if (Bits[" << Target << "::" + << Instance << "]) " << Attribute << " = " << Value << ";\n"; else - OS << " if ((Bits & " << Target << "::" - << Instance << ") != 0 && " + OS << " if (Bits[" << Target << "::" + << Instance << "] && " << Attribute << " < " << Value << ") " << Attribute << " = " << Value << ";\n"; } @@ -1418,7 +1415,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "#undef GET_SUBTARGETINFO_ENUM\n"; OS << "namespace llvm {\n"; - Enumeration(OS, "SubtargetFeature", true); + Enumeration(OS, "SubtargetFeature"); OS << "} // End llvm namespace \n"; OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; -- 2.34.1