From d3f2a4ef9ec51c27b330f2689d366c1e8f84ce78 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 13 Jan 2017 09:44:14 +0800 Subject: [PATCH] Revert "UPSTREAM: PCI: rockchip: Add quirk to disable RC's ASPM L0s" This reverts commit 6c71bcdab9b48258ab496218581d035afb65e0dd. As it was dropped from pci-next and we have another rework there. Change-Id: Icaf9d7a7fbdca5ab39b550dd0a5031fd0d3770d0 Signed-off-by: Shawn Lin --- Documentation/devicetree/bindings/pci/rockchip-pcie.txt | 2 -- drivers/pci/host/pcie-rockchip.c | 9 --------- 2 files changed, 11 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt index 5d23902863ed..71aeda1ca055 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt @@ -45,8 +45,6 @@ Required properties: Optional Property: - ep-gpios: contain the entry for pre-reset gpio - num-lanes: number of lanes to use -- quirk,aspm-no-l0s: RC won't support ASPM L0s. This property is needed if - using 24MHz OSC for RC's PHY. - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe. diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 390e8dffe6f9..0652d37a8c3f 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -145,8 +145,6 @@ #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 -#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) -#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) @@ -666,13 +664,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP); - /* Clear L0s from RC's link cap */ - if (of_property_read_bool(dev->of_node, "quirk,apsm-no-l0s")) { - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); - status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); - } - rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); rockchip_pcie_write(rockchip, -- 2.34.1