From d447ac6c8c962e62712cfe9dc1c0b940a5619163 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 13 Jul 2011 20:21:31 +0000 Subject: [PATCH] Fix encoding of predicate bits on ARM BX_pred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135076 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 7c0199dfeee..4a576e619a5 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1378,9 +1378,8 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { let Inst{3-0} = dst; } - // For disassembly only. - def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br, - "bx$p\t$dst", [/* pattern left blank */]>, + def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, + "bx", "\t$dst", [/* pattern left blank */]>, Requires<[IsARM, HasV4T]> { bits<4> dst; let Inst{27-4} = 0b000100101111111111110001; -- 2.34.1