From d457e6e9a5cd975baf4d1f0578382ab8373e6153 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 7 Nov 2009 04:04:34 +0000 Subject: [PATCH] Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseInstrInfo.cpp | 33 +++++++++++++++++++++++ lib/Target/ARM/ARMBaseInstrInfo.h | 3 +++ lib/Target/ARM/README.txt | 5 ++++ lib/Target/ARM/Thumb2InstrInfo.cpp | 26 ------------------ lib/Target/ARM/Thumb2InstrInfo.h | 4 --- test/CodeGen/Thumb/machine-licm.ll | 41 +++++++++++++++++++++++++++++ test/CodeGen/Thumb2/machine-licm.ll | 1 + 7 files changed, 83 insertions(+), 30 deletions(-) create mode 100644 test/CodeGen/Thumb/machine-licm.ll diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 7c5b0f0bd83..4915d014fec 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -14,11 +14,13 @@ #include "ARMBaseInstrInfo.h" #include "ARM.h" #include "ARMAddressingModes.h" +#include "ARMConstantPoolValue.h" #include "ARMGenInstrInfo.inc" #include "ARMMachineFunctionInfo.h" #include "ARMRegisterInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" @@ -895,6 +897,37 @@ ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, return false; } +bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0, + const MachineInstr *MI1, + const MachineRegisterInfo *MRI) const { + int Opcode = MI0->getOpcode(); + if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) { + if (MI1->getOpcode() != Opcode) + return false; + if (MI0->getNumOperands() != MI1->getNumOperands()) + return false; + + const MachineOperand &MO0 = MI0->getOperand(1); + const MachineOperand &MO1 = MI1->getOperand(1); + if (MO0.getOffset() != MO1.getOffset()) + return false; + + const MachineFunction *MF = MI0->getParent()->getParent(); + const MachineConstantPool *MCP = MF->getConstantPool(); + int CPI0 = MO0.getIndex(); + int CPI1 = MO1.getIndex(); + const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; + const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; + ARMConstantPoolValue *ACPV0 = + static_cast(MCPE0.Val.MachineCPVal); + ARMConstantPoolValue *ACPV1 = + static_cast(MCPE1.Val.MachineCPVal); + return ACPV0->hasSameValue(ACPV1); + } + + return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI); +} + /// getInstrPredicate - If instruction is predicated, returns its predicate /// condition, otherwise returns AL. It also returns the condition code /// register by reference. diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index be81bebcd66..0ccca078db4 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -263,6 +263,9 @@ public: MachineInstr* MI, const SmallVectorImpl &Ops, MachineInstr* LoadMI) const; + + virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other, + const MachineRegisterInfo *MRI) const; }; static inline diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt index fb64d9fb4ce..e4c7e6b5a6d 100644 --- a/lib/Target/ARM/README.txt +++ b/lib/Target/ARM/README.txt @@ -591,3 +591,8 @@ http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-June/022763.html //===---------------------------------------------------------------------===// Make use of the "rbit" instruction. + +//===---------------------------------------------------------------------===// + +Take a look at test/CodeGen/Thumb2/machine-licm.ll. ARM should be taught how +to licm and cse the unnecessary load from cp#1. diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index cdb06cbd957..da8ceb462b0 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -175,32 +175,6 @@ void Thumb2InstrInfo::reMaterialize(MachineBasicBlock &MBB, NewMI->getOperand(0).setSubReg(SubIdx); } -bool Thumb2InstrInfo::isIdentical(const MachineInstr *MI0, - const MachineInstr *MI1, - const MachineRegisterInfo *MRI) const { - unsigned Opcode = MI0->getOpcode(); - if (Opcode == ARM::t2LDRpci_pic) { - const MachineOperand &MO0 = MI0->getOperand(1); - const MachineOperand &MO1 = MI1->getOperand(1); - if (MO0.getOffset() != MO1.getOffset()) - return false; - - const MachineFunction *MF = MI0->getParent()->getParent(); - const MachineConstantPool *MCP = MF->getConstantPool(); - int CPI0 = MO0.getIndex(); - int CPI1 = MO1.getIndex(); - const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; - const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; - ARMConstantPoolValue *ACPV0 = - static_cast(MCPE0.Val.MachineCPVal); - ARMConstantPoolValue *ACPV1 = - static_cast(MCPE1.Val.MachineCPVal); - return ACPV0->hasSameValue(ACPV1); - } - - return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI); -} - void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, diff --git a/lib/Target/ARM/Thumb2InstrInfo.h b/lib/Target/ARM/Thumb2InstrInfo.h index 2f25e917843..456e827ba2d 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.h +++ b/lib/Target/ARM/Thumb2InstrInfo.h @@ -54,10 +54,6 @@ public: unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig) const; - bool isIdentical(const MachineInstr *MI, - const MachineInstr *Other, - const MachineRegisterInfo *MRI) const; - /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). diff --git a/test/CodeGen/Thumb/machine-licm.ll b/test/CodeGen/Thumb/machine-licm.ll new file mode 100644 index 00000000000..dae1412b913 --- /dev/null +++ b/test/CodeGen/Thumb/machine-licm.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s +; rdar://7353541 +; rdar://7354376 + +; The generated code is no where near ideal. It's not recognizing the two +; constantpool entries being loaded can be merged into one. + +@GV = external global i32 ; [#uses=2] + +define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind { +entry: +; CHECK: t: + %0 = icmp eq i32 %c, 0 ; [#uses=1] + br i1 %0, label %return, label %bb.nph + +bb.nph: ; preds = %entry +; CHECK: BB#1 +; CHECK: ldr.n r2, LCPI1_0 +; CHECK: add r2, pc +; CHECK: ldr r{{[0-9]+}}, [r2] +; CHECK: LBB1_2 +; CHECK: LCPI1_0: +; CHECK-NOT: LCPI1_1: +; CHECK: .section + %.pre = load i32* @GV, align 4 ; [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; [#uses=1] + %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; [#uses=2] + %scevgep = getelementptr i32* %vals, i32 %i.03 ; [#uses=1] + %2 = load i32* %scevgep, align 4 ; [#uses=1] + %3 = add nsw i32 %1, %2 ; [#uses=2] + store i32 %3, i32* @GV, align 4 + %4 = add i32 %i.03, 1 ; [#uses=2] + %exitcond = icmp eq i32 %4, %c ; [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 65e1369320b..912939bf24e 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s ; rdar://7353541 +; rdar://7354376 ; The generated code is no where near ideal. It's not recognizing the two ; constantpool entries being loaded can be merged into one. -- 2.34.1