From d4d25daaff1ca522b2a88b69abc956d5cba0fc30 Mon Sep 17 00:00:00 2001 From: cym Date: Mon, 13 May 2013 16:40:25 +0800 Subject: [PATCH] RK3188:ddr_clock select GPLL_2_div if ddr_freq big then 250MHz, only use for DPLL bad and ddr_clock must select GPLL(800MHz-1000MHz). --- arch/arm/mach-rk30/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) mode change 100644 => 100755 arch/arm/mach-rk30/ddr.c diff --git a/arch/arm/mach-rk30/ddr.c b/arch/arm/mach-rk30/ddr.c old mode 100644 new mode 100755 index 4a15f4ccaecf..d0cd1aab40d8 --- a/arch/arm/mach-rk30/ddr.c +++ b/arch/arm/mach-rk30/ddr.c @@ -3717,7 +3717,7 @@ uint32_t ddr_change_freq(uint32_t nMHz) } else if(gpllvaluel > 800) //GPLL:800MHz-1000MHz { - if(nMHz > 300) + if(nMHz > 250) ddr_select_gpll_div=2; //DDR_CLCOK:400MHz-500MHz else ddr_select_gpll_div=4; //DDR_CLCOK:200MHz-250MHz -- 2.34.1