From d4d826e17081808fea81509a959a983ed5df1d36 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Wed, 1 Jul 2009 21:22:45 +0000 Subject: [PATCH] Fix up a comment: besides the >80col lines, the operation for this addressing mode is encoded in the second operand, not the third. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74641 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAddressingModes.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/Target/ARM/ARMAddressingModes.h b/lib/Target/ARM/ARMAddressingModes.h index bf79152093a..7dc2dca58ce 100644 --- a/lib/Target/ARM/ARMAddressingModes.h +++ b/lib/Target/ARM/ARMAddressingModes.h @@ -459,13 +459,13 @@ namespace ARM_AM { // // addrmode5 := reg +/- imm8*4 // - // The first operand is always a Reg. The third field encodes the operation - // in bit 8, the immediate in bits 0-7. + // The first operand is always a Reg. The second operand encodes the + // operation in bit 8 and the immediate in bits 0-7. // - // This can also be used for FP load/store multiple ops. The third field encodes - // writeback mode in bit 8, the number of registers (or 2 times the number of - // registers for DPR ops) in bits 0-7. In addition, bit 9-11 encodes one of the - // following two sub-modes: + // This is also used for FP load/store multiple ops. The second operand + // encodes the writeback mode in bit 8 and the number of registers (or 2 + // times the number of registers for DPR ops) in bits 0-7. In addition, + // bits 9-11 encode one of the following two sub-modes: // // IA - Increment after // DB - Decrement before -- 2.34.1