From d726549fadb3a4578d4076c54f605743a3ed0754 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=BB=84=E6=B6=9B?= <huangtao@rock-chips.com>
Date: Sat, 2 Apr 2011 17:49:14 +0800
Subject: [PATCH] rk29: L2 Data RAM latency set to 5 cycles, suggested by zcs

---
 arch/arm/mm/proc-v7.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7a246d5c268c..f5e368dc0912 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -272,7 +272,7 @@ __v7_setup:
 	bic	r5, r5, #7 << 6
 	bic	r5, r5, #15
 	orr	r5, r5, #3 << 6			@ Tag RAM latency: b011 = 4 cycles
-	orr	r5, r5, #8			@ Data RAM latency: b1000 = 9 cycles
+	orr	r5, r5, #4			@ Data RAM latency: b0100 = 5 cycles
 	mcr	p15, 1, r5, c9, c0, 2
 #endif
 
-- 
2.34.1