From d7cc7fcf15d1daab687962d11be8abfb5226b1ce Mon Sep 17 00:00:00 2001 From: hjc Date: Mon, 18 Aug 2014 18:53:40 +0800 Subject: [PATCH] rk312x lcdc: fix hsync vsync den polo for HDMI --- drivers/video/rockchip/lcdc/rk312x_lcdc.c | 19 ++++++++++++++++++- drivers/video/rockchip/lcdc/rk312x_lcdc.h | 2 +- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/video/rockchip/lcdc/rk312x_lcdc.c b/drivers/video/rockchip/lcdc/rk312x_lcdc.c index c2e231c29b09..20e45b33874c 100755 --- a/drivers/video/rockchip/lcdc/rk312x_lcdc.c +++ b/drivers/video/rockchip/lcdc/rk312x_lcdc.c @@ -44,6 +44,11 @@ module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); if (unlikely(dbg_thresd >= level)) \ printk(KERN_INFO x); } while (0) +#define grf_writel(offset, v) do { \ + writel_relaxed(v, RK_GRF_VIRT + offset); \ + dsb(); \ + } while (0) + static struct rk_lcdc_win lcdc_win[] = { [0] = { .name = "win0", @@ -841,7 +846,19 @@ static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_UV_OFFSET_EN, v_SW_UV_OFFSET_EN(0)); - } + mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL | + m_HDMI_DEN_POL; + val = v_HDMI_HSYNC_POL(screen->pin_hsync) | + v_HDMI_HSYNC_POL(screen->pin_vsync) | + v_HDMI_DEN_POL(screen->pin_den); + lcdc_msk_reg(lcdc_dev, INT_SCALER, mask, val); + } else { + mask = (1 << 4) | (1 << 5) | (1 << 6); + val = (screen->pin_hsync << 4) | + (screen->pin_vsync << 5) | + (screen->pin_den << 6); + grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val); + } break; case SCREEN_TVOUT: mask = m_TVE_DAC_DCLK_EN; diff --git a/drivers/video/rockchip/lcdc/rk312x_lcdc.h b/drivers/video/rockchip/lcdc/rk312x_lcdc.h index f880202dde6e..07daff07abe8 100755 --- a/drivers/video/rockchip/lcdc/rk312x_lcdc.h +++ b/drivers/video/rockchip/lcdc/rk312x_lcdc.h @@ -174,7 +174,7 @@ enum _VOP_SOC_TYPE { #define v_FS_MASK_EN(x) BITS_MASK(x, 1, 3) #define v_HDMI_HSYNC_POL(x) BITS_MASK(x, 1, 4) #define v_HDMI_VSYNC_POL(x) BITS_MASK(x, 1, 5) - #define v_HDMI_DEN_POL(x) BITS_MASK(x. 1, 6) + #define v_HDMI_DEN_POL(x) BITS_MASK(x, 1, 6) #define INT_STATUS (0x10) #define m_HS_INT_STA BITS(1, 0) -- 2.34.1