From d86c0abe7fba31bbc978cf0f8efe823bf0378c65 Mon Sep 17 00:00:00 2001
From: dkl <dkl@rock-chips.com>
Date: Wed, 30 Apr 2014 18:14:35 +0800
Subject: [PATCH] rk3288: fix the bug when dclk_lcdc select gpll as parent
---
drivers/clk/rockchip/clk-ops.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 604a94f8b916..d80bff0c10d8 100644
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -572,6 +572,7 @@ static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long
if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
*best_parent_p = gpll;
best = rate;
+ *best_parent_rate = 297*MHZ;
} else {
*best_parent_p = cpll;
div = RK3288_LIMIT_PLL_VIO0/rate;
@@ -630,6 +631,7 @@ static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long
if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
*best_parent_p = gpll;
best = rate;
+ *best_parent_rate = 297*MHZ;
} else {
*best_parent_p = cpll;
div = RK3288_LIMIT_PLL_VIO1/rate;
--
2.34.1