From d8cbb1aec81a843d42bf7ffeac396f99d1f9e3a9 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 26 Sep 2016 16:31:30 +0800 Subject: [PATCH] clk: rockchip: rk3399: fix up the dclk_vop1_div parents if the dclk_vop0_div allow CLK_SET_RATE_PARENT for VPLL, the dclk_vop1_div parent is not allowed in vpll. Change-Id: I9973014e8ed2fcf1c351e3f62c00040677391ff7 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3399.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 3a4aea2b1cc1..6d8e57191829 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -173,6 +173,7 @@ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; +PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = { "dummy_vpll", "cpll", "gpll" }; /* * We hope to be able to HDMI/DP can obtain better signal quality, * therefore, we move VOP pwm and aclk clocks to other PLLs, let @@ -1219,7 +1220,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(28), 4, GFLAGS), /* The VOP1 is sub screen, it is note able to re-set parent rate. */ - COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0, + COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0, RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 13, GFLAGS), -- 2.34.1