From d8f44e07b89e651b2f0e3b0d680a775f44e667da Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Tue, 5 Sep 2006 20:19:27 +0000
Subject: [PATCH] Only call isUse/isDef on register operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30118 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/LiveVariables.cpp |  4 ++--
 lib/CodeGen/MachineInstr.cpp  | 16 +++++-----------
 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 4e5c96ec211..ddb6ded372d 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -248,7 +248,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
       // Process all explicit uses...
       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
         MachineOperand &MO = MI->getOperand(i);
-        if (MO.isUse() && MO.isRegister() && MO.getReg()) {
+        if (MO.isRegister() && MO.isUse() && MO.getReg()) {
           if (MRegisterInfo::isVirtualRegister(MO.getReg())){
             HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
           } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
@@ -268,7 +268,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
       // Process all explicit defs...
       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
         MachineOperand &MO = MI->getOperand(i);
-        if (MO.isDef() && MO.isRegister() && MO.getReg()) {
+        if (MO.isRegister() && MO.isDef() && MO.getReg()) {
           if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
             VarInfo &VRInfo = getVarInfo(MO.getReg());
 
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 480364a2821..182e664e675 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -158,7 +158,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
   unsigned StartOp = 0;
 
    // Specialize printing if op#0 is definition
-  if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
+  if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
     ::print(getOperand(0), OS, TM);
     OS << " = ";
     ++StartOp;   // Don't print this operand again!
@@ -176,11 +176,8 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
     OS << " ";
     ::print(mop, OS, TM);
 
-    if (mop.isDef())
-      if (mop.isUse())
-        OS << "<def&use>";
-      else
-        OS << "<def>";
+    if (mop.isReg() && mop.isDef())
+      OS << "<def>";
   }
 
   OS << "\n";
@@ -204,11 +201,8 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
 
   for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
     os << "\t" << MI.getOperand(i);
-    if (MI.getOperand(i).isDef())
-      if (MI.getOperand(i).isUse())
-        os << "<d&u>";
-      else
-        os << "<d>";
+    if (MI.getOperand(i).isReg() && MI.getOperand(i).isDef())
+      os << "<d>";
   }
 
   return os << "\n";
-- 
2.34.1