From d94b6a16fec7d5021e3922b0e34f9ddb268d54b1 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Fri, 4 Jan 2008 23:57:37 +0000 Subject: [PATCH] Move some more functionality from MRegisterInfo to TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/LinkAllPasses.h | 1 + include/llvm/Target/MRegisterInfo.h | 21 ------------- include/llvm/Target/TargetInstrInfo.h | 21 +++++++++++++ include/llvm/Transforms/Scalar.h | 6 ++++ lib/Target/ARM/ARMInstrInfo.cpp | 45 +++++++++++++++++++++++++++ lib/Target/ARM/ARMInstrInfo.h | 6 ++++ lib/Target/ARM/ARMRegisterInfo.cpp | 44 -------------------------- lib/Target/ARM/ARMRegisterInfo.h | 8 ----- lib/Target/IA64/IA64RegisterInfo.h | 6 ---- lib/Target/X86/X86InstrInfo.cpp | 41 ++++++++++++++++++++++++ lib/Target/X86/X86InstrInfo.h | 9 ++++++ lib/Target/X86/X86RegisterInfo.cpp | 33 -------------------- lib/Target/X86/X86RegisterInfo.h | 10 +----- 13 files changed, 130 insertions(+), 121 deletions(-) diff --git a/include/llvm/LinkAllPasses.h b/include/llvm/LinkAllPasses.h index 75ab81e83af..dd943af4c89 100644 --- a/include/llvm/LinkAllPasses.h +++ b/include/llvm/LinkAllPasses.h @@ -46,6 +46,7 @@ namespace { (void) llvm::createAliasDebugger(); (void) llvm::createAndersensPass(); (void) llvm::createArgumentPromotionPass(); + (void) llvm::createAutoVectorizePass(); (void) llvm::createBasicAliasAnalysisPass(); (void) llvm::createBasicVNPass(); (void) llvm::createBlockPlacementPass(); diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 05ba3851b9a..1faa0b50120 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -25,7 +25,6 @@ namespace llvm { class BitVector; -class CalleeSavedInfo; class MachineFunction; class MachineInstr; class MachineLocation; @@ -470,26 +469,6 @@ public: // immediates and memory. FIXME: Move these to TargetInstrInfo.h. // - /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee - /// saved registers and returns true if it isn't possible / profitable to do - /// so by issuing a series of store instructions via - /// storeRegToStackSlot(). Returns false otherwise. - virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const { - return false; - } - - /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee - /// saved registers and returns true if it isn't possible / profitable to do - /// so by issuing a series of load instructions via loadRegToStackSlot(). - /// Returns false otherwise. - virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const { - return false; - } - /// getCrossCopyRegClass - Returns a legal register class to copy a register /// in the specified class to or from. Returns NULL if it is possible to copy /// between a two registers of the specified class. diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 7d0ba7eadd4..5ba1204609a 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -26,6 +26,7 @@ class MachineInstr; class TargetMachine; class TargetRegisterClass; class LiveVariables; +class CalleeSavedInfo; template class SmallVectorImpl; @@ -497,6 +498,26 @@ public: assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); } + /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee + /// saved registers and returns true if it isn't possible / profitable to do + /// so by issuing a series of store instructions via + /// storeRegToStackSlot(). Returns false otherwise. + virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + return false; + } + + /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee + /// saved registers and returns true if it isn't possible / profitable to do + /// so by issuing a series of load instructions via loadRegToStackSlot(). + /// Returns false otherwise. + virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + return false; + } + /// BlockHasNoFallThrough - Return true if the specified block does not /// fall-through into its successor block. This is primarily used when a /// branch is unanalyzable. It is useful for things like unconditional diff --git a/include/llvm/Transforms/Scalar.h b/include/llvm/Transforms/Scalar.h index f1a101f6028..0fbc72f0a34 100644 --- a/include/llvm/Transforms/Scalar.h +++ b/include/llvm/Transforms/Scalar.h @@ -330,6 +330,12 @@ FunctionPass *createPredicateSimplifierPass(); // FunctionPass *createGVNPREPass(); +//===----------------------------------------------------------------------===// +// +// AutoVectorize - This pass performs vectorization of straight-line code +// +FunctionPass *createAutoVectorizePass(); + //===----------------------------------------------------------------------===// // // GVN - This pass performs global value numbering and redundant load diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index ef92c3d223d..b608d5f81e4 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -18,6 +18,7 @@ #include "ARMMachineFunctionInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/Target/TargetAsmInfo.h" @@ -598,6 +599,50 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, return; } +bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + MachineFunction &MF = *MBB.getParent(); + ARMFunctionInfo *AFI = MF.getInfo(); + if (!AFI->isThumbFunction() || CSI.empty()) + return false; + + MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH)); + for (unsigned i = CSI.size(); i != 0; --i) { + unsigned Reg = CSI[i-1].getReg(); + // Add the callee-saved register as live-in. It's killed at the spill. + MBB.addLiveIn(Reg); + MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); + } + return true; +} + +bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + MachineFunction &MF = *MBB.getParent(); + ARMFunctionInfo *AFI = MF.getInfo(); + if (!AFI->isThumbFunction() || CSI.empty()) + return false; + + bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; + MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP)); + MBB.insert(MI, PopMI); + for (unsigned i = CSI.size(); i != 0; --i) { + unsigned Reg = CSI[i-1].getReg(); + if (Reg == ARM::LR) { + // Special epilogue for vararg functions. See emitEpilogue + if (isVarArg) + continue; + Reg = ARM::PC; + PopMI->setInstrDescriptor(get(ARM::tPOP_RET)); + MBB.erase(MI); + } + PopMI->addOperand(MachineOperand::CreateReg(Reg, true)); + } + return true; +} + bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index ff96b3d33f9..a1cd8216191 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -184,6 +184,12 @@ public: SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; + virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const; + virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector &Cond) const; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 6054699089f..b940052de9b 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -88,50 +88,6 @@ ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) { } -bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const { - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo(); - if (!AFI->isThumbFunction() || CSI.empty()) - return false; - - MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH)); - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - // Add the callee-saved register as live-in. It's killed at the spill. - MBB.addLiveIn(Reg); - MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); - } - return true; -} - -bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const { - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo(); - if (!AFI->isThumbFunction() || CSI.empty()) - return false; - - bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; - MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP)); - MBB.insert(MI, PopMI); - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - if (Reg == ARM::LR) { - // Special epilogue for vararg functions. See emitEpilogue - if (isVarArg) - continue; - Reg = ARM::PC; - PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET)); - MBB.erase(MI); - } - PopMI->addOperand(MachineOperand::CreateReg(Reg, true)); - } - return true; -} - static inline const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { return MIB.addImm((int64_t)ARMCC::AL).addReg(0); diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h index 1ee07436b97..8ca7a9d337d 100644 --- a/lib/Target/ARM/ARMRegisterInfo.h +++ b/lib/Target/ARM/ARMRegisterInfo.h @@ -37,14 +37,6 @@ public: static unsigned getRegisterNumbering(unsigned RegEnum); /// Code Generation virtual methods... - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const; - - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const; - void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h index 0782e8a3051..6e682e3eefd 100644 --- a/lib/Target/IA64/IA64RegisterInfo.h +++ b/lib/Target/IA64/IA64RegisterInfo.h @@ -29,12 +29,6 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo { IA64RegisterInfo(const TargetInstrInfo &tii); /// Code Generation virtual methods... - void copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const; - void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 577b9374901..3d876c28371 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -15,9 +15,11 @@ #include "X86.h" #include "X86GenInstrInfo.inc" #include "X86InstrBuilder.h" +#include "X86MachineFunctionInfo.h" #include "X86Subtarget.h" #include "X86TargetMachine.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/LiveVariables.h" @@ -962,6 +964,45 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, NewMIs.push_back(MIB); } +bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + if (CSI.empty()) + return false; + + bool is64Bit = TM.getSubtarget().is64Bit(); + unsigned SlotSize = is64Bit ? 8 : 4; + + MachineFunction &MF = *MBB.getParent(); + X86MachineFunctionInfo *X86FI = MF.getInfo(); + X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); + + unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; + for (unsigned i = CSI.size(); i != 0; --i) { + unsigned Reg = CSI[i-1].getReg(); + // Add the callee-saved register as live-in. It's killed at the spill. + MBB.addLiveIn(Reg); + BuildMI(MBB, MI, get(Opc)).addReg(Reg); + } + return true; +} + +bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + if (CSI.empty()) + return false; + + bool is64Bit = TM.getSubtarget().is64Bit(); + + unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + BuildMI(MBB, MI, get(Opc), Reg); + } + return true; +} + bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 280d040c6ad..d39b8659e1f 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -296,6 +296,15 @@ public: SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; + + virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const; + + virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const; + virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector &Cond) const; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index f86d5a00c55..49effcf0167 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -741,39 +741,6 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { } } -bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const { - if (CSI.empty()) - return false; - - MachineFunction &MF = *MBB.getParent(); - X86MachineFunctionInfo *X86FI = MF.getInfo(); - X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); - unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r; - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - // Add the callee-saved register as live-in. It's killed at the spill. - MBB.addLiveIn(Reg); - BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg); - } - return true; -} - -bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const { - if (CSI.empty()) - return false; - - unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r; - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - BuildMI(MBB, MI, TII.get(Opc), Reg); - } - return true; -} - static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB, MachineOperand &MO) { if (MO.isRegister()) diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 0695b3fe616..de348d7d6bb 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -92,15 +92,7 @@ public: int getDwarfRegNum(unsigned RegNum, bool isEH) const; /// Code Generation virtual methods... - /// - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const; - - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const; - + /// const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const; -- 2.34.1