From d9593dbc0386e6b29fc98d8e03c6533ad74e4838 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E8=AE=B8=E7=9B=9B=E9=A3=9E?= <xsf@rock-chips.com>
Date: Tue, 8 Jul 2014 19:43:32 +0800
Subject: [PATCH] rk3036: add pwm-pinctrl

---
 arch/arm/boot/dts/rk3036-pinctrl.dtsi | 30 +++++++++++++++++++++++++++
 arch/arm/boot/dts/rk3036.dtsi         | 16 +++++++-------
 2 files changed, 38 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/rk3036-pinctrl.dtsi b/arch/arm/boot/dts/rk3036-pinctrl.dtsi
index 96cda83ef149..75ef0830a27e 100755
--- a/arch/arm/boot/dts/rk3036-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rk3036-pinctrl.dtsi
@@ -501,6 +501,36 @@
                                         //rockchip,tristate = <VALUE_TRI_DEFAULT>;
                                 };
                 };
+		gpio0_pwm{
+
+                  	pwm0_pin:pwm0 {
+                                rockchip,pins = <PWM0>;
+                                rockchip,pull = <VALUE_PULL_DISABLE>;
+                                rockchip,drive = <VALUE_DRV_DEFAULT>;
+                                //rockchip,tristate = <VALUE_TRI_DEFAULT>;
+                        };
+
+                        pwm1_pin:pwm1 {
+                                rockchip,pins = <PWM1>;
+                                rockchip,pull = <VALUE_PULL_DISABLE>;
+                                rockchip,drive = <VALUE_DRV_DEFAULT>;
+                                //rockchip,tristate = <VALUE_TRI_DEFAULT>;
+                        };
+
+                        pwm2_pin:pwm2 {
+                                rockchip,pins = <PWM2>;
+                                rockchip,pull = <VALUE_PULL_DISABLE>;
+                                rockchip,drive = <VALUE_DRV_DEFAULT>;
+                                //rockchip,tristate = <VALUE_TRI_DEFAULT>;
+                        };
+                  	
+			pwm3_pin:pwm3 {
+                                rockchip,pins = <PWM3(IR)>;
+                                rockchip,pull = <VALUE_PULL_DISABLE>;
+                                rockchip,drive = <VALUE_DRV_DEFAULT>;
+                                //rockchip,tristate = <VALUE_TRI_DEFAULT>;
+                        };
+		};
 
 		vol_domain {
 			ap0_vcc:ap0-vcc {
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 9da50489462e..8e49b79881d0 100755
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -339,8 +339,8 @@
 		compatible = "rockchip,rk-pwm";
 		reg = <0x20050000 0x10>;
 		#pwm-cells = <2>;
-		//pinctrl-names = "default";
-		//pinctrl-0 = <&pwm_pin>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm0_pin>;
 		clocks = <&clk_gates7 10>;
 		clock-names = "pclk_pwm";
 		status = "disabled";
@@ -350,8 +350,8 @@
                 compatible = "rockchip,rk-pwm";
                 reg = <0x20050010 0x10>;
                 #pwm-cells = <2>;
-                //pinctrl-names = "default";
-                //pinctrl-0 = <&pwm_pin>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm1_pin>;
                 clocks = <&clk_gates7 10>;
                 clock-names = "pclk_pwm";
                 status = "disabled";
@@ -361,8 +361,8 @@
                 compatible = "rockchip,rk-pwm";
                 reg = <0x20050020 0x10>;
                 #pwm-cells = <2>;
-                //pinctrl-names = "default";
-                //pinctrl-0 = <&pwm_pin>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm2_pin>;
                 clocks = <&clk_gates7 10>;
                 clock-names = "pclk_pwm";
                 status = "disabled";
@@ -372,8 +372,8 @@
                 compatible = "rockchip,rk-pwm";
                 reg = <0x20050030 0x10>;
                 #pwm-cells = <2>;
-                //pinctrl-names = "default";
-                //pinctrl-0 = <&pwm_pin>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm3_pin>;
                 clocks = <&clk_gates7 10>;
                 clock-names = "pclk_pwm";
                 status = "disabled";
-- 
2.34.1