From d9a31f9ee045d91983f55ac5961ababcb7de8142 Mon Sep 17 00:00:00 2001 From: Feng Xiao Date: Thu, 17 Mar 2016 09:50:36 +0800 Subject: [PATCH] ARM64: dts: rockchip: rk3399: add cpu dvfs support for tb Change-Id: I707ebf8b4ba045401ebb3e609d511a8eb0883120 Signed-off-by: Feng Xiao --- arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi | 24 ++++++++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 62 +++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi index 4befd7177e67..1f0d29190ed0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi @@ -362,3 +362,27 @@ &pwm0 { status = "okay"; }; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index b9f935bf08e1..fe4429a7eba3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -106,24 +106,32 @@ reg = <0x0 0x0>; #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster0_opp>; }; cpu_l1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster0_opp>; }; cpu_l2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster0_opp>; }; cpu_l3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster0_opp>; }; cpu_b0: cpu@100 { @@ -132,12 +140,66 @@ reg = <0x0 0x100>; #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKB>; + operating-points-v2 = <&cluster1_opp>; }; cpu_b1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x101>; + clocks = <&cru ARMCLKB>; + operating-points-v2 = <&cluster1_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; }; }; -- 2.34.1