From d9e5c764bfea339fc5082bf17e558db959fd6d28 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 5 Jan 2012 00:26:49 +0000 Subject: [PATCH] Freeze reserved registers before starting register allocation. The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147577 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/ReleaseNotes.html | 4 +++ include/llvm/CodeGen/MachineRegisterInfo.h | 39 +++++++++++++++++++++- lib/CodeGen/MachineRegisterInfo.cpp | 4 +++ lib/CodeGen/RegAllocBasic.cpp | 1 + lib/CodeGen/RegAllocFast.cpp | 1 + lib/CodeGen/RegAllocPBQP.cpp | 1 + 6 files changed, 49 insertions(+), 1 deletion(-) diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html index 7dd0b8d5506..011cbbd344c 100644 --- a/docs/ReleaseNotes.html +++ b/docs/ReleaseNotes.html @@ -351,6 +351,10 @@ Release Notes. represent combinations of constraints from instructions and sub-registers. The synthetic register classes inherit most of their properties form their closest user-defined super-class. +
  • MachineRegisterInfo now allows the reserved registers to be + frozen when register allocation starts. Target hooks should use the + MRI->canReserveReg(FramePtr) method to avoid accidentally + disabling frame pointer elimination during register allocation.
    • diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h index 773683a7480..34d454ebc9c 100644 --- a/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/include/llvm/CodeGen/MachineRegisterInfo.h @@ -57,7 +57,13 @@ class MachineRegisterInfo { /// so that the code generator knows which callee save registers to save and /// for other target specific uses. BitVector UsedPhysRegs; - + + /// ReservedRegs - This is a bit vector of reserved registers. The target + /// may change its mind about which registers should be reserved. This + /// vector is the frozen set of reserved registers when register allocation + /// started. + BitVector ReservedRegs; + /// LiveIns/LiveOuts - Keep track of the physical registers that are /// livein/liveout of the function. Live in values are typically arguments in /// registers, live out values are typically return values in registers. @@ -309,6 +315,37 @@ public: /// subregisters. That means that if R is used, so are all subregisters. void closePhysRegsUsed(const TargetRegisterInfo&); + + //===--------------------------------------------------------------------===// + // Reserved Register Info + //===--------------------------------------------------------------------===// + // + // The set of reserved registers must be invariant during register + // allocation. For example, the target cannot suddenly decide it needs a + // frame pointer when the register allocator has already used the frame + // pointer register for something else. + // + // These methods can be used by target hooks like hasFP() to avoid changing + // the reserved register set during register allocation. + + /// freezeReservedRegs - Called by the register allocator to freeze the set + /// of reserved registers before allocation begins. + void freezeReservedRegs(const MachineFunction&); + + /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called + /// to ensure the set of reserved registers stays constant. + bool reservedRegsFrozen() const { + return !ReservedRegs.empty(); + } + + /// canReserveReg - Returns true if PhysReg can be used as a reserved + /// register. Any register can be reserved before freezeReservedRegs() is + /// called. + bool canReserveReg(unsigned PhysReg) const { + return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); + } + + //===--------------------------------------------------------------------===// // LiveIn/LiveOut Management //===--------------------------------------------------------------------===// diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index c35b154aa1a..67291a0eb8c 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -259,3 +259,7 @@ void MachineRegisterInfo::dumpUses(unsigned Reg) const { I.getOperand().getParent()->dump(); } #endif + +void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { + ReservedRegs = TRI->getReservedRegs(MF); +} diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp index 5496d69fd3d..8019cf227bd 100644 --- a/lib/CodeGen/RegAllocBasic.cpp +++ b/lib/CodeGen/RegAllocBasic.cpp @@ -233,6 +233,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) { MRI = &vrm.getRegInfo(); VRM = &vrm; LIS = &lis; + MRI->freezeReservedRegs(vrm.getMachineFunction()); RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); const unsigned NumRegs = TRI->getNumRegs(); diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index c2656c5e5c8..93f39b6c661 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -1047,6 +1047,7 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) { TM = &Fn.getTarget(); TRI = TM->getRegisterInfo(); TII = TM->getInstrInfo(); + MRI->freezeReservedRegs(Fn); RegClassInfo.runOnMachineFunction(Fn); UsedInInstr.resize(TRI->getNumRegs()); diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index a053cccc9e0..f8b0b9fa6eb 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -619,6 +619,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { vrm = &getAnalysis(); spiller.reset(createInlineSpiller(*this, MF, *vrm)); + mri->freezeReservedRegs(MF); DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n"); -- 2.34.1