From da21bb714ed141a24d6d080f406d61bbfd273135 Mon Sep 17 00:00:00 2001 From: Huang Jiachai Date: Thu, 3 Dec 2015 15:06:56 +0800 Subject: [PATCH] ARM64: dts: add display node for rk3368 tb Change-Id: I574d6773598abe81b55760c438c34ef911660406 Signed-off-by: Huang Jiachai --- arch/arm64/boot/dts/rockchip/rk3368-tb.dts | 45 ++++++++++ arch/arm64/boot/dts/rockchip/rk3368.dtsi | 98 ++++++++++++++++++++++ 2 files changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-tb.dts b/arch/arm64/boot/dts/rockchip/rk3368-tb.dts index fc164573fa87..ab70d9eba52a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-tb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-tb.dts @@ -268,3 +268,48 @@ &uart2 { status = "okay"; }; + +&fb { + rockchip,disp-mode = ; + rockchip,uboot-logo-on = <0>; +}; + +&rk_screen { + /*#include */ + #include +}; + +&lcdc { + status = "okay"; + backlight = <&backlight>; + rockchip,mirror = ; + rockchip,cabc_mode = <0>; + rockchip,fb-win-map = ; + power_ctr: power_ctr { + rockchip,debug = <0>; + lcd_en:lcd_en { + rockchip,power_type = ; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;/*GPIO_C6 = 22*/ + rockchip,delay = <10>; + }; + + lcd_cs:lcd_cs { + rockchip,power_type = ; + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;/*GPIO_C5 = 21*/ + rockchip,delay = <10>; + }; + + /*lcd_rst:lcd_rst { + rockchip,power_type = ; + gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>; + rockchip,delay = <5>; + };*/ + }; +}; + +&lvds { + status = "disabled"; + pinctrl-names = "lcdc", "sleep"; + pinctrl-0 = <&lcdc_lcdc>; + pinctrl-1 = <&lcdc_gpio>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index ac49a12b9191..e494eb768e5f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3368"; @@ -67,6 +68,7 @@ spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; + lcdc = &lcdc; }; cpus { @@ -1039,6 +1041,102 @@ rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; }; }; + + lcdc { + lcdc_lcdc: lcdc-lcdc { + rockchip,pins = + <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10 + <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11 + <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12 + <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13 + <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14 + <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15 + <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16 + <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17 + <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18 + <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19 + <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20 + <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21 + <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22 + <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23 + <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK + <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN + <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC + <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN + }; + + lcdc_gpio: lcdc-gpio { + rockchip,pins = + <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10 + <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11 + <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12 + <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13 + <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14 + <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15 + <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16 + <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17 + <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18 + <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19 + <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20 + <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21 + <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22 + <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23 + <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK + <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN + <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC + <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN + }; + }; + }; + + fb: fb { + compatible = "rockchip,rk-fb"; + rockchip,disp-mode = ; + }; + + rk_screen: rk_screen { + compatible = "rockchip,screen"; + }; + + lcdc: lcdc@ff930000 { + compatible = "rockchip,rk3368-lcdc"; + rockchip,grf = <&grf>; + rockchip,pmugrf = <&pmugrf>; + rockchip,cru = <&cru>; + rockchip,prop = ; + rockchip,pwr18 = <0>; + rockchip,iommu-enabled = <1>; + reg = <0x0 0xff930000 0x0 0x10000>; + interrupts = ; + status = "disabled"; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; + /*power-domains = <&power PD_VIO>;*/ + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + }; + + lvds: lvds@ff968000 { + compatible = "rockchip,rk3368-lvds"; + rockchip,grf = <&grf>; + reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>; + reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; + clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>; + clock-names = "pclk_lvds", "pclk_lvds_ctl"; + /*power-domains = <&power PD_VIO>;*/ + status = "disabled"; + }; + + edp: edp@ff970000 { + compatible = "rockchip,rk32-edp"; + reg = <0x0 0xff970000 0x0 0x4000>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; + clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; + /*power-domains = <&power PD_VIO>;*/ + resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>; + reset-names = "edp_24m", "edp_apb"; }; iep_mmu { -- 2.34.1