From da771ed4109a2f548507e23cfde830478f42e53a Mon Sep 17 00:00:00 2001 From: Yakir Yang Date: Fri, 18 Mar 2016 16:19:21 +0800 Subject: [PATCH] ARM64: dts: rk3399: add eDP device node Change-Id: I0b1bb874b51f45d71f63445cb30c43f94b022c20 Signed-off-by: Yakir Yang --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 52 ++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 4e5e3edda6dc..6321750a7fca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1022,6 +1022,11 @@ #address-cells = <1>; #size-cells = <0>; + vopl_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_in_vopl>; + }; + vopl_out_mipi: endpoint@1 { reg = <1>; remote-endpoint = <&mipi_in_vopl>; @@ -1053,6 +1058,11 @@ #address-cells = <1>; #size-cells = <0>; + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_in_vopb>; + }; + vopb_out_mipi: endpoint@1 { reg = <1>; remote-endpoint = <&mipi_in_vopb>; @@ -1102,6 +1112,41 @@ }; }; + edp: edp@ff970000 { + compatible = "rockchip,rk3399-edp"; + reg = <0x0 0xff970000 0x0 0x8000>; + interrupts = ; + clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + resets = <&cru SRST_P_EDP_CTRL>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + display_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vopl_out>, <&vopb_out>; @@ -1743,5 +1788,12 @@ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = + <4 23 RK_FUNC_2 &pcfg_pull_none>; + }; + }; }; }; -- 2.34.1