From da813f420907ad29802ce9e80238258a48385212 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Wed, 28 Dec 2011 21:24:44 +0000 Subject: [PATCH] Fix type-checking for load transformation which is not legal on floating-point types. PR11674. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 3 ++- test/CodeGen/X86/vec_fpext.ll | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/vec_fpext.ll diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 00b46d2cf67..28cd252ce81 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -13924,7 +13924,8 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, // shuffle. We need SSE4 for the shuffles. // TODO: It is possible to support ZExt by zeroing the undef values // during the shuffle phase or after the shuffle. - if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { + if (RegVT.isVector() && RegVT.isInteger() && + Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { assert(MemVT != RegVT && "Cannot extend to the same type"); assert(MemVT.isVector() && "Must load a vector from memory"); diff --git a/test/CodeGen/X86/vec_fpext.ll b/test/CodeGen/X86/vec_fpext.ll new file mode 100644 index 00000000000..05b263e2e0c --- /dev/null +++ b/test/CodeGen/X86/vec_fpext.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86 -mattr=+sse41,-avx | FileCheck %s + +; PR11674 +define void @fpext_frommem(<2 x float>* %in, <2 x double>* %out) { +entry: +; TODO: We should be able to generate cvtps2pd for the load. +; For now, just check that we generate something sane. +; CHECK: cvtss2sd +; CHECK: cvtss2sd + %0 = load <2 x float>* %in, align 8 + %1 = fpext <2 x float> %0 to <2 x double> + store <2 x double> %1, <2 x double>* %out, align 1 + ret void +} -- 2.34.1